SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

• US 20170077069A1
• Filed: 07/15/2016
• Published: 03/16/2017
• Est. Priority Date: 09/11/2015
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: DANNO, Tadatoshi, NISHIKIZAWA, Atsushi
• Granted Patent: US 9,735,127 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05014 being square
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4903 Connectors having different sizes, e.g. different diameters
• CPC Class Codes: H01L 2224/49107 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/047 the other leads being parallel to the base
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/3677 : Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/49503 : characterised by the die pad
• CPC Class Codes: H01L 23/49513 : having bonding material between chip and die pad
• CPC Class Codes: H01L 23/49548 : Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49555 : the bent parts being the outer leads
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49844 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15159 : Side view
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H05K 1/0206 : by printed thermal vias

Abstract

An improvement is achieved in the reliability of a semiconductor device. Over a die pad, first and second semiconductor chips are mounted. The first and second semiconductor chips and a part of the die pad are sealed in a sealing portion. The first semiconductor chip includes a power transistor. The second semiconductor chip controls the first semiconductor chip. The thickness of the portion of the die pad over which the first semiconductor chip is mounted is smaller than the thickness of the portion of the die pad over which the second semiconductor chip is mounted.

Claims

1. A semiconductor device, comprising:

a chip mounting portion;

a first semiconductor chip mounted over the chip mounting portion and including a power transistor;

a second semiconductor chip mounted over the chip mounting portion to control the first semiconductor chip; and

a sealing body sealing therein the first and second semiconductor chips and at least a part of the chip mounting portion,

wherein a first thickness of a first portion of the chip mounting portion over which the first semiconductor chip is mounted is smaller than a second thickness of a second portion of the chip mounting portion over which the second semiconductor chip is mounted.

2. The semiconductor device according to claim 1, further comprising:

a plurality of leads; and

a plurality of wires,

wherein the sealing body seals therein the wires and a part of each of the leads, and

wherein the wires include a plurality of first wires electrically coupling a plurality of first pad electrodes of the first semiconductor chip to a plurality of first leads which are among the leads and a plurality of second wires electrically coupling a plurality of second pad electrodes of the second semiconductor chip to a plurality of second leads which are among the leads.

3. The semiconductor device according to claim 2,

wherein the second thickness of the second portion is equal to a third thickness of each of the leads.

4. The semiconductor device according to claim 1,

wherein a fourth thickness of the first semiconductor chip is smaller than a fifth thickness of the second semiconductor chip.

5. The semiconductor device according to claim 1,

wherein the first semiconductor chip is mounted over the chip mounting portion via a first junction layer, and

wherein the second semiconductor chip is mounted over the chip mounting portion via a second junction layer.

6. The semiconductor device according to claim 5,

wherein a sixth thickness of the first junction layer between the chip mounting portion and the first semiconductor chip is smaller than a seventh thickness of the first junction layer between the chip mounting portion and the first semiconductor chip.

7. The semiconductor device according to claim 5,

wherein a heat conductivity of the first junction layer is higher than a heat conductivity of the second junction layer.

8. A semiconductor device, comprising:

a chip mounting portion;

a first semiconductor chip mounted over the chip mounting portion;

a second semiconductor chip mounted over the chip mounting portion; and

a sealing body sealing therein the first and second semiconductor chips and at least a part of the chip mounting portion,

wherein an amount of heat generated in the first semiconductor chip during an operation thereof is larger than an amount of heat generated in the second semiconductor chip during an operation thereof, and

wherein a thickness of a first portion of the chip mounting portion over which the first semiconductor chip is mounted is smaller than a thickness of a second portion of the chip mounting portion over which the second semiconductor chip is mounted.

9. The semiconductor device according to claim 8, further comprising:

a plurality of leads; and

a plurality of wires,

wherein the sealing body seals therein a part of each of the leads and the wires, and

wherein the wires include a plurality of first wires electrically coupling a plurality of first pad electrodes of the first semiconductor chip to a plurality of first leads which are among the leads and a plurality of second wires electrically coupling a plurality of second pad electrodes of the second semiconductor chip to a plurality of second leads which are among the leads.

10. The semiconductor device according to claim 9,

wherein the thickness of the second portion is equal to a thickness of each of the leads.

11. An electronic device, comprising:

a wiring substrate; and

a semiconductor device mounted over a first main surface of the wiring substrate,

wherein the semiconductor device includes;

a chip mounting portion having a second main surface and a third main surface opposite to the second main surface;

a first semiconductor chip mounted over the second main surface of the chip mounting portion and including a power transistor;

a second semiconductor chip mounted over the second main surface of the chip mounting portion to control the first semiconductor chip; and

a sealing body sealing therein the first and second semiconductor chips and at least a part of the chip mounting portion,

wherein the third main surface of the chip mounting portion of the semiconductor device is exposed from the sealing body,

wherein the wiring substrate has first and second electrodes formed over the first main surface and isolated from each other,

wherein a first portion of the chip mounting portion is bonded to the first electrode via a first conductive bonding layer,

wherein a second portion of the chip mounting portion is bonded to the second electrode via a second conductive bonding layer,

wherein the first semiconductor chip is mounted over the first portion of the chip mounting portion, and

wherein the second semiconductor chip is mounted over the second portion of the chip mounting portion.

12. The electronic device according to claim 11,

wherein, in plan view, the first semiconductor chip has at least a part thereof overlapping the first electrode and does not overlap the second electrode, and

wherein, in plan view, the second semiconductor chip has at least a part thereof overlapping the second electrode and does not overlap the first electrode.

13. The electronic device according to claim 11,

wherein, in plan view, the first semiconductor chip is included in the first electrode, and

wherein, in plan view, the second semiconductor chip is included in the second electrode.

14. The electronic device according to claim 11,

wherein a first thickness of the chip mounting portion immediately under the first semiconductor chip is smaller than a second thickness of the chip mounting portion immediately under the second semiconductor chip.

15. The electronic device according to claim 11,

wherein the semiconductor device further includes:

a plurality of leads; and

a plurality of wires,

wherein the sealing body seals therein at least a part of each of the leads and the wires,

wherein the wires include a plurality of first wires electrically coupling a plurality of first pad electrodes of the first semiconductor chip to a plurality of first leads which are among the leads and a plurality of second wires electrically coupling a plurality of second pad electrodes of the second semiconductor chip to a plurality of second leads which are among the leads,

wherein the wiring substrate further has a plurality of third electrodes formed over the first main surface, and

wherein the leads are bonded individually to the third electrodes.

16. The electronic device according to claim 15,

wherein the second thickness of the second portion is equal to a third thickness of each of the leads.

17. The electronic device according to claim 11,

wherein the wiring substrate further has a conductor pattern in a layer located below that of each of the first and second electrodes, and

wherein the first electrode is electrically coupled to the conductor pattern via a plurality of first via portions disposed under the first electrode.

18. The electronic device according to claim 17,

wherein, under the second electrode, a via portion which electrically couples the second electrode to the conductor pattern is not formed.

19. The electronic device according to claim 17,

wherein the second electrode is electrically coupled to the conductor pattern via a plurality of second via portions disposed under the second electrode.