Semiconductor Device and Method for Manufacturing the Same

• US 20170077150A1
• Filed: 11/23/2016
• Published: 03/16/2017
• Est. Priority Date: 05/05/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kimura, Hajime
• Granted Patent: US 10,283,530 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate electrode, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are provided over the second insulating layer. The first gate electrode has a region overlapping with the semiconductor layer with the first insulating layer provided therebetween. The second gate electrode has a region overlapping with the semiconductor layer with the second insulating layer provided therebetween. A first region is at least part of a region where the second gate electrode overlaps with the semiconductor layer. A second region is at least part of a region where the pixel electrode is provided. The second insulating layer is thinner in the first region than in the second region.

Claims

1. (canceled)

2. A semiconductor device comprising:

a gate electrode over a substrate;

a first insulating layer over the gate electrode;

an oxide semiconductor layer over the first insulating layer, the oxide semiconductor layer overlapping with the gate electrode;

a first conductive layer and a second conductive layer over the oxide semiconductor layer, the first conductive layer and the second conductive layer electrically connected to the oxide semiconductor layer;

a second insulating layer over the oxide semiconductor layer, the first conductive layer, and the second conductive layer, the second insulating layer including a first opening;

a third insulating layer over the second insulating layer, the third insulating layer including a second opening;

a fourth insulating layer over the third insulating layer, the fourth insulating layer including a third opening; and

a pixel electrode over the fourth insulating layer, the pixel electrode electrically connected to the first conductive layer through the first opening, the second opening, and the third opening,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc,

wherein the second insulating layer comprises silicon and nitrogen,

wherein the third insulating layer comprises an organic material,

wherein the fourth insulating layer comprises silicon and nitrogen,

wherein the third insulating layer is thicker than the second insulating layer,

wherein the third insulating layer is thicker than the fourth insulating layer,

wherein a width of each of the first opening and the third opening is smaller than a width of the second opening,

wherein the pixel electrode is in contact with a side surface of the second insulating layer in the first opening, and

wherein the pixel electrode is in contact with a side surface of the fourth insulating layer in the third opening.

3. The semiconductor device according to claim 2, further comprising:

a third conductive layer over the fourth insulating layer, the third conductive layer overlapping with the oxide semiconductor layer.

4. The semiconductor device according to claim 2,

wherein the third insulating layer further includes a fourth opening,

wherein the fourth opening overlaps with the oxide semiconductor layer, and

wherein the second insulating layer is in contact with the fourth insulating layer in the fourth opening.

5. The semiconductor device according to claim 2, further comprising:

a fifth insulating layer between the oxide semiconductor layer and each of the first conductive layer and the second conductive layer.

6. The semiconductor device according to claim 2, wherein the pixel electrode does not overlap with the oxide semiconductor layer.

7. The semiconductor device according to claim 2, wherein the oxide semiconductor layer includes a crystal with c-axis alignment.

8. A semiconductor device comprising:

a gate electrode over a substrate;

a first insulating layer over the gate electrode;

an oxide semiconductor layer over the first insulating layer, the oxide semiconductor layer overlapping with the gate electrode;

a first conductive layer and a second conductive layer over the oxide semiconductor layer, the first conductive layer and the second conductive layer electrically connected to the oxide semiconductor layer;

a second insulating layer over the oxide semiconductor layer, the first conductive layer, and the second conductive layer, the second insulating layer including a first opening;

a third insulating layer over the second insulating layer, the third insulating layer including a second opening;

a fourth insulating layer over the third insulating layer, the fourth insulating layer including a third opening; and

a pixel electrode over the fourth insulating layer, the pixel electrode electrically connected to the first conductive layer through the first opening, the second opening, and the third opening,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc,

wherein the second insulating layer comprises silicon and nitrogen,

wherein the third insulating layer comprises an organic material,

wherein the fourth insulating layer comprises silicon and nitrogen,

wherein the third insulating layer is thicker than the second insulating layer,

wherein the third insulating layer is thicker than the fourth insulating layer,

wherein a width of each of the first opening and the third opening is smaller than a width of the second opening,

wherein the pixel electrode is in contact with a side surface of the second insulating layer in the first opening,

wherein the pixel electrode is in contact with a side surface of the fourth insulating layer in the third opening, and

wherein the third opening overlaps with the oxide semiconductor layer.

9. The semiconductor device according to claim 8, further comprising:

a third conductive layer over the fourth insulating layer, the third conductive layer overlapping with the oxide semiconductor layer.

10. The semiconductor device according to claim 8,

wherein the third insulating layer further includes a fourth opening,

wherein the fourth opening overlaps with the oxide semiconductor layer, and

wherein the second insulating layer is in contact with the fourth insulating layer in the fourth opening.

11. The semiconductor device according to claim 8, further comprising:

a fifth insulating layer between the oxide semiconductor layer and each of the first conductive layer and the second conductive layer.

12. The semiconductor device according to claim 8, wherein the pixel electrode does not overlap with the oxide semiconductor layer.

13. The semiconductor device according to claim 8, wherein the oxide semiconductor layer includes a crystal with c-axis alignment.

14. The semiconductor device according to claim 8, wherein a side surface of the oxide semiconductor layer is in contact with the second insulating layer.

15. The semiconductor device according to claim 8, wherein a side surface of the oxide semiconductor layer extends to a side surface of the first conductive layer.