METHOD OF MANUFACTURING SEMICONDUCTOR UNIT AND THE SEMICONDUCTOR UNIT

• US 20170077165A1
• Filed: 07/03/2016
• Published: 03/16/2017
• Est. Priority Date: 09/10/2015
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: KIMURA, Masatoshi
• Granted Patent: US 9,793,311 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/14607 Geometry of the photosensitive area
• CPC Class Codes: H01L 27/1461 characterised by the photosensitive area
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

In a solid-state imaging device including a plurality of pixels each pixel including a plurality of photodiodes, it is prevented that an incidence angle of incident light on the solid-state imaging device becomes large in a pixel in an end of the solid-state imaging device, causing a difference in output between the two photodiodes in the pixel, and thus autofocus detection accuracy is deteriorated. Photodiodes extending in a longitudinal direction of a pixel allay section are provided in each pixel. The photodiodes in the pixel are arranged in a direction orthogonal to the longitudinal direction of the pixel allay section.

Claims

1. A semiconductor unit including a solid-state imaging device including a plurality of pixels each including two photodiodes, the semiconductor unit comprising:

a semiconductor substrate;

a pixel array section extending in a first direction along a main surface of the semiconductor substrate over the main surface of the semiconductor substrate;

the pixels provided in the pixel array section; and

the two photodiodes provided in the main surface of the semiconductor substrate in each of the pixels,

wherein the two photodiodes are arranged in a second direction orthogonal to the first direction in the pixel.

2. The semiconductor unit according to claim 1, wherein each of the two photodiodes extends in the first direction.

3. The semiconductor unit according to claim 1, further comprising gate electrodes that are provided over the semiconductor substrate and are adjacent to the two respective photodiodes in plan view,

wherein the two photodiodes are located close to the center of the pixel array section in the first direction with respect to the gate electrodes.

4. A semiconductor unit including a solid-state imaging device including pixels each including a first photodiode and a second photodiode, the semiconductor unit comprising:

a semiconductor substrate;

a pixel array section extending in a first direction along a main surface of the semiconductor substrate over the main surface of the semiconductor substrate;

the pixels provided in the pixel array section;

a first semiconductor region having a first conductivity type and a second semiconductor region having the first conductivity type arranged separately from each other in the first direction in the main surface of the semiconductor substrate in each of the pixels;

the first photodiode including the first semiconductor region;

the second photodiode including the second semiconductor region; and

a third semiconductor region having a second conductivity type different from the first conductivity type provided in the main surface of the semiconductor substrate and between the first photodiode and the second photodiode,

wherein a first pixel among the pixels is located near an end of the pixel array section in the first direction, and width of the first photodiode in the first pixel is smaller than width in the first direction of the second photodiode in the first pixel.

5. The semiconductor unit according to claim 4, wherein the center in the first direction of the third semiconductor region in the first pixel is located closer to the end than the center in the first direction of a region including the first photodiode and the second photodiode in the first pixel.

6. The semiconductor unit according to claim 4, wherein the first photodiode and the third semiconductor region in the first pixel are in contact with each other in plan view, and the second photodiode and the third semiconductor region in the first pixel are in contact with each other in plan view.

7. The semiconductor unit according to claim 4, further comprising an element isolating region surrounding the first photodiode and the second photodiode of each of the pixels in plan view,

wherein a shortest distance in the first direction between the first photodiode provided closer to the end than the second photodiode in the first pixel and the element isolating region is smaller than a shortest distance in the first direction between the first photodiode provided closer to the end than the second photodiode in a second pixel among the pixels, the second pixel being located in a central portion in the first direction of the pixel array section, and the element isolating region.

8. The semiconductor unit according to claim 7, further comprising:

a well region having the second conductivity type in contact with the first semiconductor region and the second semiconductor region so as to cover the first semiconductor region and the second semiconductor region in the semiconductor substrate; and

a fourth semiconductor region having the second conductivity type provided in a surface of the semiconductor substrate in contact with the element isolating region,

wherein impurity concentration of the fourth semiconductor region is higher than impurity concentration of the well region, and

wherein the first photodiode in the first pixel is in contact with the fourth semiconductor region in plan view.

9. A method of manufacturing a semiconductor unit comprising a solid-state imaging device including a plurality of pixels in a pixel array section, each pixel including a first photodiode and a second photodiode, the method comprising the steps of:

(a) providing a semiconductor substrate;

(b) forming a well region having a first conductivity type in a main surface of the semiconductor substrate;

(c) after the step (b), forming a first semiconductor region having the first conductivity type in the main surface of the semiconductor substrate, the first semiconductor region extending in a first direction along the main surface of the semiconductor substrate; and

(d) forming a second semiconductor region having a second conductivity type different from the first conductivity type in a top of the well region while the second semiconductor region overlaps with some of the first semiconductor region in plan view,

wherein the second semiconductor region in contact with a first end as one end of the first semiconductor region in the first direction configures the first photodiode, and the second semiconductor region in contact with a second end as the other end of the first semiconductor region in the first direction configures the second photodiode, and

wherein a first pixel among the pixels is located near a third end of the pixel array section in a second direction orthogonal to the first direction, and width in the second direction of the first photodiode in the first pixel is smaller than width in the second direction of the second photodiode in the first pixel.

10. The method according to claim 9, further comprising the step of:

(b1) after the step (b) and before the step (c), forming an element isolating region surrounding an active region,

wherein in each of the pixels, the first photodiode and the second photodiode are provided in the active region, and

wherein a shortest distance in the second direction between the first photodiode formed closer to the third end than the second photodiode and the element isolating region in the first pixel is smaller than a shortest distance in the second direction between the first photodiode formed closer to the third end than the second photodiode and the element isolating region in a second pixel among the pixels, the second pixel being located in a central portion in the second direction of the pixel array section.

11. The method according to claim 10, further comprising the step of:

(b2) after the step (b), forming a third semiconductor region having the first conductivity type and having an impurity concentration higher than an impurity concentration of the well region in a surface of the semiconductor substrate in contact with the element isolating region,

wherein in the first pixel, part of a region forming the third semiconductor region overlaps with part of a region forming the second semiconductor region on a side close to the third end in plan view.

12. The method according to claim 10,

wherein in the step (d), two semiconductor regions, each semiconductor region being the second semiconductor region, arranged separately from each other in the second direction are formed, and

wherein in the two second semiconductor regions, one second semiconductor region is in contact with the first end of the first semiconductor region, and the other second semiconductor region is in contact with the second end of the first semiconductor region.

13. The method according to claim 12, wherein width in the second direction of a first region in which a region forming one second semiconductor region of the two second semiconductor regions, the one second semiconductor region being located close to the third end, overlaps with a region forming the first semiconductor region is larger than width in the second direction of a second region in which a region forming the other second semiconductor region of the two second semiconductor regions overlaps with the region forming the first semiconductor region.

14. The method according to claim 12, wherein the pixel array section extends in the second direction.