FINFET DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20170077228A1
• Filed: 09/10/2015
• Published: 03/16/2017
• Est. Priority Date: 09/10/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LI, Chii-Horng, KUO, Chien-I, TING, Heng-Wen, TAI, Jung-Chi, SU, Lilly, HSIAO, Yang-Tai, LEE, Yen-Ru
• Granted Patent: US 10,103,249 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins and a source/drain structure. The semiconductor fins and the source/drain structure are located on the semiconductor substrate, and the source/drain structure is connected to the semiconductor fins. The source/drain structure has a top portion with a W-shape cross section for forming a contact landing region. The semiconductor device may further include a plurality of capping layers located on a plurality of recessed portions of the top portion.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a source structure located on the semiconductor substrate;

a drain structure located on the semiconductor substrate; and

a plurality of semiconductor fins protruding from the semiconductor substrate, wherein the semiconductor fins are spaced apart from each other, and connect the source structure and the drain structure;

wherein each of the source structure and the drain structure has a top portion with a W-shape cross section for forming a contact landing region.

2. The semiconductor device of claim 1, wherein the top portion has a plurality of protrusive portions corresponding to the semiconductor fins in a one-to-one manner.

3. The semiconductor device of claim 1, wherein heights of the protrusive portions are greater than or equal to heights of the semiconductor fins.

4. The semiconductor device of claim 1, wherein the top portion comprises a plurality of recessed portions, and each of the recessed portion has a side wall inclined at an angle relative to horizontal, and the angle is in a range substantially from 30 degrees to 65 degrees.

5. The semiconductor device of claim 1, further comprising a plurality of capping layers located in a plurality of recessed portions of the top portion.

6. The semiconductor device of claim 5, wherein the capping layers comprise a low concentration III-V semiconductor, and each of the source structure and the drain structure comprises a high concentration III-V semiconductor.

7. The semiconductor device of claim 6, wherein the capping layers are lightly impurity-doped, and each of the source structure and the drain structure is heavily impurity-doped.

8. The semiconductor device of claim 7, wherein a thickness of each of the capping layers is in a range substantially from 2 nm to 10 nm.

9. A fin field-effect transistor (FinFET) device, comprising:

a semiconductor substrate;

a plurality of source/drain structures located on the semiconductor substrate wherein each of the source/drain structures has a top portion with a W-shape cross section for forming a contact landing region;

a plurality of semiconductor fins protruding from the semiconductor substrate and connecting the source/drain structures; and

a plurality of gate structures disposed across the semiconductor fins, wherein each of the gate structures comprises a gate electrode stack and spacers located on sidewalls of the gate electrode stack.

10. The FinFET device of claim 9, wherein the top portion has a plurality of protrusive portions corresponding to the semiconductor fins in a one-to-one manner.

11. The FinFET device of claim 9, wherein heights of the protrusive portions match heights of the semiconductor fins.

12. The FinFET device of claim 9, wherein the top portion comprises a plurality of recessed portions, and each of the recessed portion has a side wall inclined at an angle relative to horizontal, and the angle is in a range substantially from 30 degrees to 65 degrees.

13. The FinFET device of claim 9, further comprising a plurality of capping layers located in a plurality of recessed portions of the top portion.

14. The FinFET device of claim 13, wherein the capping layers comprise a low concentration III-V semiconductor, and the source/drain structure comprises a high concentration III-V semiconductor.

15. The FinFET device of claim 14, wherein the capping layers are lightly impurity-doped, and the source/drain structure is heavily impurity-doped.

16. The FinFET of claim 15, wherein a thickness of each of the capping layers is in a range substantially from 2 nm to 10 nm.

17. The FinFET device of claim 9, wherein the spacers are formed by silicon nitride.

18. A method for fabricating a FinFET device, comprising:

providing a semiconductor substrate;

forming a plurality of semiconductor fins protruding from the semiconductor substrate;

forming a plurality of source/drain structures on the semiconductor substrate; and

connecting the source/drain structures;

wherein each of the source/drain structures has a top portion with a W-shape cross section for forming a contact landing region.

19. The method of claim 18, further comprising:

forming a capping layer to cover all of the source/drain structure; and

etching a portion of the capping layer to expose the source/drain structure with another portion of the capping layer remaining.

20. The method of claim 18, further comprising:

forming a capping layer conformal to the source/drain structure; and

etching a portion of the capping layer to expose the source/drain structure with another portion of the capping layer remaining.