SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD

• US 20170077274A1
• Filed: 09/05/2016
• Published: 03/16/2017
• Est. Priority Date: 09/16/2015
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: NAITO, Tatsuya
• Granted Patent: US 10,505,028 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/083 Anode or cathode regions of thyristors or gated bipolar-mode devices
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A semiconductor device including a semiconductor substrate; a trench formed in a front surface of the semiconductor substrate; a gate conducting portion formed within the gate trench; and a first region formed adjacent to the trench in the front surface of the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate. A shoulder portion is provided on a side wall of the gate trench between the top end of the gate conducting portion and the front surface of the semiconductor substrate and has an average slope, relative to a depth direction of the semiconductor substrate, that is greater than a slope of the side wall of the gate trench at a position opposite the top end of the gate conducting portion, and a portion of the first region that contacts the gate trench is formed as a deepest portion thereof.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a gate trench that is formed in a front surface of the semiconductor substrate;

a gate conducting portion that is formed within the gate trench, provided such that a top end thereof is at a deeper position than the front surface of the semiconductor substrate, and insulated from the semiconductor substrate; and

a first region that is formed adjacent to the gate trench in the front surface of the semiconductor substrate and has a higher impurity concentration than the semiconductor substrate, wherein

a shoulder portion is provided on a side wall of the gate trench between the top end of the gate conducting portion and the front surface of the semiconductor substrate and has an average slope, relative to a depth direction of the semiconductor substrate, that is greater than a slope of the side wall of the gate trench at a position opposite the top end of the gate conducting portion, and

a portion of the first region that contacts the gate trench is formed as a deepest portion of the first region.

2. The semiconductor device according to claim 1, wherein

the shoulder portion has a convex curved surface portion that protrudes toward the inside of the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein

the portion of the first region contacting the gate trench is a longest portion of the first region in the depth direction.

4. The semiconductor device according to claim 1, wherein

a portion of an end surface of the gate conducting portion on the front surface side of the semiconductor substrate that is adjacent to the side wall of the gate trench is a portion of the end surface of the gate conducting portion formed closest to the front surface of the semiconductor substrate.

5. The semiconductor device according to claim 1, wherein

the side wall of the gate trench has a portion forming an angle greater than or equal to 20 degrees relative to the depth direction of the semiconductor substrate at the shoulder portion.

6. The semiconductor device according to claim 1, wherein

the gate trench is provided extending in a predetermined extension direction in the front surface of the semiconductor substrate,

a plurality of the first regions and a plurality of second regions, which have a different conduction type than the first region, are provided in an alternating manner in the extension direction in a region adjacent to the gate trench in the front surface of the semiconductor substrate, and

a plurality of the shoulder portions are provided respectively in both a sidewall of the gate trench adjacent to a first region and a side wall of the gate trench adjacent to a second region.

7. The semiconductor device according to claim 6, wherein

portions of the second regions that contact the gate trench are formed as the deepest portions of the second regions.

8. The semiconductor device according to claim 1, wherein

a plurality of the gate trenches that each have different distances from the front surface of the semiconductor substrate to the top end of the gate conducting portion are formed in the semiconductor substrate,

depth of the first region adjacent to a gate trench having a greater distance from the front surface of the semiconductor substrate to the top end of the gate conducting portion is greater than depth of the first region adjacent to a gate trench having a smaller distance from the front surface of the semiconductor substrate to the top end of the gate conducting portion.

9. The semiconductor device according to claim 8, wherein

the semiconductor substrate further includes a third region that is formed on the back surface side of each of the first regions, has a different conduction type than the first regions, and has a bottom end with a uniform depth.

10. The semiconductor device according to claim 1, wherein

the gate trench is provided extending in a predetermined extension direction in the front surface of the semiconductor substrate,

the first region is provided along the extension direction in a region adjacent to the gate trench in the front surface of the semiconductor substrate, and

the semiconductor device further comprises:

a third region that is formed below the first region in the semiconductor substrate and has a different conduction type than the first region;

a plug that penetrates through the first region and has a bottom end arranged within the third region; and

a second region that is formed in contact with the bottom end of the plug in the third region, has the same conduction type as the third region, and has a higher impurity concentration than the third region.

11. The semiconductor device according to claim 10, further comprising:

an accumulation region that is formed below the third region in the semiconductor substrate and has a higher impurity concentration than the semiconductor substrate.

12. A manufacturing method for manufacturing a semiconductor device, comprising:

forming a gate trench in a front surface of a semiconductor substrate;

forming a gate conducting portion that is provided within the gate trench, has a top end that is provided at a position deeper than the front surface of the semiconductor substrate, and is insulated from the semiconductor substrate; and

forming a first region that is adjacent to the gate trench in the front surface of the semiconductor substrate and has a higher impurity concentration than the semiconductor substrate, by using the gate conducting portion as a mask and injecting impurities into a side wall of the gate trench, wherein

the forming the gate trench includes providing, on a side wall of the gate trench between the top end of the gate conducting portion and the front surface of the semiconductor substrate, a shoulder portion that has an average slope, relative to a depth direction of the semiconductor substrate, that is greater than a slope of the side wall of the gate trench at a position opposite the top end of the gate conducting portion, and

a portion of the first region that contacts the gate trench is formed as a deepest portion of the first region.

13. The manufacturing method according to claim 12, wherein

the forming the first region includes injecting impurities into the side wall of the gate trench from a direction having a slope relative to the depth direction of the semiconductor substrate.

14. The manufacturing method according to claim 12, wherein

the forming the gate trench and the forming the gate conducting portion include forming, in the semiconductor substrate, a plurality of the gate trenches that have different distances from the front surface of the semiconductor substrate to the top end of the gate conducting portion, and

the forming the first region includes forming the first region with a depth corresponding to the distance from the front surface of the semiconductor substrate to the top end of the gate conducting portion.

15. The manufacturing method according to claim 14, wherein

the forming the gate trench includes forming a plurality of the gate trenches with different depths, and

the forming the gate conducting portion includes forming a plurality of the gate conducting portions with the same length respectively in the gate trenches.