SIGNAL PROCESSING SYSTEM AND ASSOCIATED METHOD

• US 20170077947A1
• Filed: 11/22/2016
• Published: 03/16/2017
• Est. Priority Date: 03/07/2013
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Yang, Chien-Chung, Chiang, Chia-Feng, Chen, Chien-Ming
• Granted Patent: US 9,800,263 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1443 Transmit or communication errors
• CPC Class Codes: G06F 11/3041 where the computing system component is an input/output interface interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units G06F13/00
• CPC Class Codes: G06F 11/3051 Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs verification or detection of system hardware configuration G06F11/2247
• CPC Class Codes: G06F 13/10 Program control for peripheral devices G06F13/14 - G06F13/42 take precedence
• CPC Class Codes: G06F 13/12 using hardware independent of the central processor, e.g. channel or peripheral processor
• CPC Class Codes: G06F 3/00 Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
• CPC Class Codes: H03M 3/462 Details relating to the decimation process decimation filters in general H03H17/0416, H03H17/0621
• CPC Class Codes: H03M 3/50 Digital/analogue converters using delta-sigma modulation as an intermediate step digital delta-sigma modulators per se H03M7/3004
• CPC Class Codes: H03M 3/508 Details relating to the interpolation process

Abstract

The present invention provides a signal processing system and associated method. The signal processing system includes converter(s) for conversion between digital and analog, each converter includes multiple serially coupled units forming multiple frequency interfaces respectively associating with different frequencies, and each converter is partitioned, at a selected frequency interface, to a first portion and a second portion respectively formed in the first chip and the second chip. The partitioning frequency interface is selected to reduce implement cost.

Claims

1. A signal processing system distributed across a first chip and a second chip, comprising:

a first inter-chip connection circuit formed in the first chip,

a second inter-chip connection circuit formed in the second chip and coupled to the first inter-chip connection circuit, and

a quantity of converters for conversion between digital and analog;

each of the quantity of converters comprising;

a first portion comprising a plurality of serially coupled units forming a plurality of frequency interfaces, different ones of the frequency interfaces respectively associating with different frequencies, and each said unit converting frequencies between two consecutive ones of the frequency interfaces; and

a second portion converting between analog and an intermediate digital signal associated with a terminal one of the frequency interfaces;

wherein said first portion and said second portion of each said converter are respectively formed in the first chip and the second chip, and the first inter-chip connection circuit and the second inter-chip connection circuit are arranged to relay signaling between said first portion and said second portion of each said converter.

2. The signal processing system of claim 1, the quantity of converters including a digital-to-analog converter (DAC) for converting a main digital signal to a main analog signal, and said second portion of the DAC comprising:

a DAC interface circuit coupled to a last one of said units of the DAC via the first inter-chip connection circuit and the second inter-chip connection circuit, and

a DAC stage coupled to the DAC interface circuit;

wherein a first one of said units of the DAC receives the main digital signal and accordingly provides a signal of a higher sampling frequency, each of said units following the first one of said units receives a signal provided by a preceding one of said units and accordingly provides another signal of a higher sampling frequency to a successive one of said units, and the last one of said units receives a signal provided by a preceding one of said units and accordingly provides said intermediate digital signal of a higher sampling frequency;

the DAC interface circuit modulates said intermediate signal of the DAC to form a modulated signal by sigma-delta modulation, and the DAC stage converts the modulated signal to the main analog signal.

3. The signal processing system of claim 1, the quantity of converters including an analog-to-digital converter (ADC);

the ADC converting a main analog signal to a main digital signal, and said second portion of the ADC comprising;

an ADC interface circuit coupled to a first one of said units of the ADC via the first inter-chip connection circuit and the second inter-chip connection circuit, providing said intermediate digital signal in response to the main analog signal by sigma-delta modulation;

wherein the first one of said units of the ADC receives said intermediate signal of the ADC and accordingly provides a signal of a lower sampling frequency, each of said units between the first one and a last one of said units receives a signal provided by a preceding one of said units and accordingly provides another signal of a lower sampling frequency to a successive one of said units, and the last one of said units receives a signal provided by a preceding one of said units and accordingly provides the main digital signal of a lower sampling frequency.

4. The signal processing system of claim 1, wherein:

the quantity of converters include a first number of first kind converters,

said first portion of each first kind converter, according to said intermediate digital signal of each first kind converter, provides a first transmitting signal to be transferred to said second portion of each first kind converter,

the first inter-chip connection circuit arranges samples in the first number of said first transmitting signals to form a first amount of first streams, and transmits the first amount of first streams respectively via a same amount of first data balls of the first inter-chip connection circuit, and

the second inter-chip connection circuit receives the first amount of first streams via a same amount of second data balls of the second inter-chip connection circuit respectively coupled to the first amount of first data balls, rearranges samples in the first amount of first streams, and accordingly obtains the first number of said first transmitting signals for the first number of said second portions of the first number of first kind converters.

5. The signal processing system of claim 4, wherein

the first inter-chip connection circuit further adds error correction information to the first amount of first streams according to the first number of said first transmitting signals, and

the second inter-chip connection circuit further corrects the received first amount of first streams in response to the error correction information while obtaining the first number of said first transmitting signals.

6. The signal processing system of claim 4, wherein:

each first kind converter further comprises;

a first encoding stage in said first portion of each first kind converter, and

a first decoding stage in said second portion of each first kind converter;

wherein the first encoding stage of each first kind converter encodes said intermediate digital signal of each first kind converter to provide a first encoded signal as said first transmitting signal of each first kind converter;

the first decoding stage of each first kind converter decodes an associated one of the first number of said first transmitting signals obtained by the second inter-chip connection circuit to obtain said intermediate signal for said second portion of each first kind converter.

7. The signal processing system of claim 4, wherein:

the quantity of converters further includes a second number of second kind converters,

said second portion of each second kind converter, according to said intermediate digital signal of each second kind converter, provides a second transmitting signal to be transferred to said first portion of each second kind converter,

the second inter-chip connection circuit further arranges samples in the second number of said second transmitting signals to form a second amount of second streams with the second amount equal to the first amount, and transmits the second amount of second streams respectively via the first amount of second data balls, and

the first inter-chip connection circuit further receives the second amount of second streams from the first amount of first data balls, rearranges samples in the second amount of second streams, and accordingly obtains the second number of said second transmitting signals for the second number of said first portions of the second number of second kind converters.

8. The signal processing system of claim 7, wherein

the second inter-chip connection circuit further adds second error correction information to the second amount of second streams according to the second number of said second transmitting signals, and

the first inter-chip connection circuit further corrects the received second amount of second streams in response to the second error correction information while obtaining the second number of said second transmitting signals.

9. The signal processing system of claim 7, wherein:

each second kind converter further comprises;

a second encoding stage in said second portion of each second kind converter, and

a second decoding stage in said first portion of each second kind converter;

wherein the second encoding stage of each second kind converter encodes said intermediate digital signal of each second kind converter to provide a second encoded signal as said second transmitting signal of each second kind converter;

the second decoding stage of each second kind converter decodes an associated one of the second number of said second transmitting signals obtained by the first inter-chip connection circuit to obtain said intermediate digital signal for said first portion of each second kind converter.

10. A signal processing system distributed across a first chip and a second chip, comprising:

a first inter-chip connection circuit formed in the first chip,

a second inter-chip connection circuit formed in the second chip and coupled to the first inter-chip connection circuit, and

a quantity of converters;

each of the quantity of converters converting between a main digital signal and a main analog signal, and comprising;

a first portion comprising a plurality of serially coupled units forming a plurality of frequency interfaces, different ones of the frequency interfaces respectively associating with different frequencies, and each said unit converting frequencies between two consecutive ones of the frequency interfaces, such that the plurality of units collectively convert between the main digital signal and an intermediate digital signal of two different sampling frequencies; and

a second portion converting between the intermediate digital signal and the main analog signal;

wherein the first portion and the second portion of each said converter are respectively formed in the first chip and the second chip, and the first inter-chip connection circuit and the second inter-chip connection circuit are arranged to relay signaling between the first portion and the second portion of each said converter.

11. The signal processing system of claim 10, the quantity of converters including a digital-to-analog converter (DAC) for converting said main digital signal of the DAC to said main analog signal of the DAC, and said second portion of the DAC comprising:

a DAC interface circuit coupled to a last one of said units of the DAC via the first inter-chip connection circuit and the second inter-chip connection circuit, and

a DAC stage coupled to the DAC interface circuit;

wherein a first one of said units of the DAC receives said main digital signal of the DAC and accordingly provides a signal of a higher sampling frequency, each of said units following the first one of said units receives a signal provided by a preceding one of said units and accordingly provides another signal of a higher sampling frequency to a successive one of said units, and the last one of said units receives a signal provided by a preceding one of said units and accordingly provides said intermediate digital signal of a higher sampling frequency;

the DAC interface circuit modulates said intermediate signal of the DAC to form a modulated signal by sigma-delta modulation, and the DAC stage converts the modulated signal to said main analog signal of the DAC.

12. The signal processing system of claim 10, the quantity of converters including an analog-to-digital converter (ADC);

the ADC converting said main analog signal of the ADC to said main digital signal of the ADC, and said second portion of the ADC comprising;

an ADC interface circuit coupled to a first one of said units of the ADC via the first inter-chip connection circuit and the second inter-chip connection circuit, providing said intermediate digital signal of the ADC in response to said main analog signal of the ADC by sigma-delta modulation;

wherein the first one of said units of the ADC receives said intermediate signal of the ADC and accordingly provides a signal of a lower sampling frequency, each of said units between the first one and a last one of said units receives a signal provided by a preceding one of said units and accordingly provides another signal of a lower sampling frequency to a successive one of said units, and the last one of said units receives a signal provided by a preceding one of said units and accordingly provides said main digital signal of a lower sampling frequency.

13. The signal processing system of claim 10, wherein:

the quantity of converters include a first number of first kind converters,

said first portion of each first kind converter, according to said intermediate digital signal of each first kind converter, provides a first transmitting signal to be transferred to said second portion of each first kind converter,

the first inter-chip connection circuit arranges samples in the first number of said first transmitting signals to form a first amount of first streams, and transmits the first amount of first streams respectively via a same amount of first data balls of the first inter-chip connection circuit, and

the second inter-chip connection circuit receives the first amount of first streams via a same amount of second data balls of the second inter-chip connection circuit respectively coupled to the first amount of first data balls, rearranges samples in the first amount of first streams, and accordingly obtains the first number of said first transmitting signals for the first number of said second portions of the first number of first kind converters.

14. The signal processing system of claim 13, wherein

the first inter-chip connection circuit further adds error correction information to the first amount of first streams according to the first number of said first transmitting signals, and

the second inter-chip connection circuit further corrects the received first amount of first streams in response to the error correction information while obtaining the first number of said first transmitting signals.

15. The signal processing system of claim 13, wherein:

each first kind converter further comprises;

a first encoding stage in said first portion of each first kind converter, and

a first decoding stage in said second portion of each first kind converter;

wherein the first encoding stage of each first kind converter encodes said intermediate digital signal of each first kind converter to provide a first encoded signal as said first transmitting signal of each first kind converter;

the first decoding stage of each first kind converter decodes an associated one of the first number of said first transmitting signals obtained by the second inter-chip connection circuit to obtain said intermediate signal for said second portion of each first kind converter.

16. The signal processing system of claim 13, wherein:

the quantity of converters further includes a second number of second kind converters,

said second portion of each second kind converter, according to said intermediate digital signal of each second kind converter, provides a second transmitting signal to be transferred to said first portion of each second kind converter,

the second inter-chip connection circuit further arranges samples in the second number of said second transmitting signals to form a second amount of second streams with the second amount equal to the first amount, and transmits the second amount of second streams respectively via the first amount of second data balls, and

the first inter-chip connection circuit further receives the second amount of second streams from the first amount of first data balls, rearranges samples in the second amount of second streams, and accordingly obtains the second number of said second transmitting signals for the second number of said first portions of the second number of second kind converters.

17. The signal processing system of claim 16, wherein

the second inter-chip connection circuit further adds second error correction information to the second amount of second streams according to the second number of said second transmitting signals, and

the first inter-chip connection circuit further corrects the received second amount of second streams in response to the second error correction information while obtaining the second number of said second transmitting signals.

18. The signal processing system of claim 16, wherein:

each second kind converter further comprises;

a second encoding stage in said second portion of each second kind converter, and

a second decoding stage in said first portion of each second kind converter;

wherein the second encoding stage of each second kind converter encodes said intermediate digital signal of each second kind converter to provide a second encoded signal as said second transmitting signal of each second kind converter;

the second decoding stage of each second kind converter decodes an associated one of the second number of said second transmitting signals obtained by the first inter-chip connection circuit to obtain said intermediate digital signal for said first portion of each second kind converter.

19. A signal processing system distributed across a first chip and a second chip, comprising:

a first inter-chip connection circuit formed in the first chip,

a second inter-chip connection circuit formed in the second chip and coupled to the first inter-chip connection circuit, and

a quantity of converters;

each of the quantity of converters converting between a main digital signal and a main analog signal, and comprising;

a first portion comprising a plurality of serially coupled units forming a plurality of frequency interfaces, different ones of the frequency interfaces respectively associating with different frequencies, and each said unit converting frequencies between two consecutive ones of the frequency interfaces, such that the plurality of units collectively convert between the main digital signal and an intermediate digital signal of two different sampling frequencies; and

a second portion converting between the main analog signal and the intermediate digital signal, and comprising;

an interface circuit converting between the intermediate digital signal and a modulation digital signal by sigma-delta modulation, and a conversion stage converting between the modulation digital signal and the main analog signal, and;

wherein the first portion and the second portion of each said converter are respectively formed in the first chip and the second chip, and the first inter-chip connection circuit and the second inter-chip connection circuit are arranged to relay signaling between the first portion and the second portion of each said converter.

20. The signal processing system of claim 19, wherein:

the quantity of converters include a first number of DACs and a second number of ADCs,

said first portion of each DAC, according to said intermediate digital signal of each DAC, provides a first transmitting signal to be transferred to said second portion of each DAC;

said second portion of each ADC, according to said intermediate digital signal of each second kind converter, provides a second transmitting signal to be transferred to said first portion of each ADC;

the first inter-chip connection circuit arranges samples in the first number of said first transmitting signals to form a first amount of first streams, and transmits the first amount of first streams respectively via a same amount of first data balls of the first inter-chip connection circuit;

the second inter-chip connection circuit receives the first amount of first streams via a same amount of second data balls of the second inter-chip connection circuit respectively coupled to the first amount of first data balls, rearranges samples in the first amount of first streams, and accordingly obtains the first number of said first transmitting signals for the first number of said second portions of the first number of DACs;

the second inter-chip connection circuit further arranges samples in the second number of said second transmitting signals to form a second amount of second streams with the second amount equal to the first amount, and transmits the second amount of second streams respectively via the first amount of second data balls; and

the first inter-chip connection circuit further receives the second amount of second streams from the first amount of first data balls, rearranges samples in the second amount of second streams, and accordingly obtains the second number of said second transmitting signals for the second number of said first portions of the second number of ADCs.