CONTINUOUS TIME LINEAR EQUALIZATION FOR CURRENT-MODE LOGIC WITH TRANSFORMER
First Claim
1. A communication system comprising:
- a pair of differential input terminals, the pair of differential input terminals comprising a first input and a second input for receiving data;
a current mode logic device comprising;
a first transistor comprising a first gate and a first output terminal and a first source terminal, the first gate being electrically coupled to the first input;
a second transistor comprising a second gate and a second output terminal, the second gate being electrically coupled to the second input;
a capacitor module coupled to the first source terminal;
a first resistor coupled to the first output terminal;
a second resistor coupled to the second output terminal;
a first transformer comprising a first primary winding and a first secondary winding, the first primary winding being electrically coupled to the first resistor and the first output terminal; and
a first equalization module coupled to the first secondary winding, the first equalization module comprising a first digital-to-analog converter (DAC) unit, the DAC unit being configure to adjust an impedance value of the first equalization module in response to an equalization signal; and
a SerDes device being coupled to the first output terminal.
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Accused Products
Abstract
The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. The equalization modules comprises a DAC component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well.
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Citations
20 Claims
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1. A communication system comprising:
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a pair of differential input terminals, the pair of differential input terminals comprising a first input and a second input for receiving data; a current mode logic device comprising; a first transistor comprising a first gate and a first output terminal and a first source terminal, the first gate being electrically coupled to the first input; a second transistor comprising a second gate and a second output terminal, the second gate being electrically coupled to the second input; a capacitor module coupled to the first source terminal; a first resistor coupled to the first output terminal; a second resistor coupled to the second output terminal; a first transformer comprising a first primary winding and a first secondary winding, the first primary winding being electrically coupled to the first resistor and the first output terminal; and a first equalization module coupled to the first secondary winding, the first equalization module comprising a first digital-to-analog converter (DAC) unit, the DAC unit being configure to adjust an impedance value of the first equalization module in response to an equalization signal; and a SerDes device being coupled to the first output terminal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for equalizing signals using a common-mode logic (CML) device, the method comprising:
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receiving a pair of differential input signals using a pair of input transistors, the pair of input transistors including a first transistor, the first transistor including a first source terminal and a first drain terminal; receiving a bias control signal; configuring a capacitor module using at least the bias control signal, the capacitor module being coupled to the first source terminal; receiving a first equalization signal; adjusting a first peaking level of a first equalizer module using the first equalization signal; adjusting a first inductance value of a first transformer using the first equalizer module, the first transformer being coupled to a first output load; and generating a first output signal based at least on the different input signal and first inductance value of the first transformer, the first output signal being coupled to the first drain terminal. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method for equalizing signals using a common-mode logic (CML) device, the method comprising:
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receiving a pair of differential input signals using a pair of input transistors, the pair of input transistors including a first transistor, the first transistor including a first source terminal and a first drain terminal; receiving a bias control signal; configuring a capacitor module using at least the bias control signal, the capacitor module being coupled to a first source terminal; receiving the first equalization signal; converting the equalization signal to a plurality of control bits using a DAC; providing an equalization module, the equalization module comprising a plurality of resistors and being coupled to a transformer; switching the plurality of resistors using the plurality of control bits; generating a first output signal based at least on the different input signal and first inductance value of the transformer, the first output signal being coupled to the first drain terminal. - View Dependent Claims (17, 18, 19, 20)
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Specification