TEST STRUCTURE, FABRICATION METHOD, AND TEST METHOD

• US 20170082678A1
• Filed: 08/16/2016
• Published: 03/23/2017
• Est. Priority Date: 09/23/2015
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: Li, Yong
• Granted Patent: US 10,078,108 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/2628 for measuring thermal properties thereof
• CPC Class Codes: G01R 31/2644 Adaptations of individual semiconductor devices to facilitate the testing thereof
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 22/10 Measuring as part of the manufacturing process burn-in G01R31/2855
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/30 Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

The present disclosure provides test structures, fabrication methods thereof and test methods thereof. An exemplary test structure includes a substrate having a to-be-tested region having at least one fin and a peripheral region having at least one fin surrounding the to-be-tested region; an insulation layer covering portions of side surfaces of the fins; at least one first gate structure covering side and top surfaces of the fin in the to-be-tested region; second gate structures covering side and top surfaces of the fins in the peripheral region; source/drain regions formed in portions of the fins between adjacent second gate structures and portions of the fins between the first gate structure and adjacent second gate structures; and a plurality of first conductive structures formed between adjacent second gate structures in the peripheral region. The plurality of first conductive structures cross over and are on source/drain regions of at least two fins.

Claims

1. A test structure, comprising:

a substrate having a to-be-tested region and a peripheral region surrounding the to-be-tested region, the to-be-tested region having at least one fin, the peripheral region having at least one fin, the at least one fin in the to-be-tested region being parallel to the at least one fin in the peripheral region, and two ends of the at least one fin in the to-be-tested region extending into the peripheral region;

an insulation layer covering portions of side surfaces of the fins;

at least one first gate structure covering side and top surfaces of the at least one fin in the to-be-tested region;

a plurality of parallel second gate structures covering side and top surfaces of the at least one fin in the peripheral region, and the second gate structures being parallel to the first gate structure;

source/drain regions formed in portions of the at least one fin between adjacent second gate structures and portions of the at least one fin between the at least one first gate structure and adjacent second gate structures; and

a plurality of first conductive structures formed between adjacent second gate structures in the peripheral region, the plurality of first conductive structures crossing over at least two fins, and the plurality of first conductive structures being on surfaces of source/drain regions of at least two fins.

2. The test structure according to claim 1, wherein in the to-be-tested region:

a number of the first gate structure is equal to or greater than 1; and

each first gate structure crosses over one or more parallel fins.

3. The test structure according to claim 2, wherein:

when the number of the first gate structure is greater than 1, the plurality of first gate structures are parallel.

4. The test structure according to claim 1, wherein:

the plurality of second gate structures cross over one or more parallel fins.

5. The test structure according to claim 1, wherein:

at least one of the plurality of second gate structures and the at least one first gate structure are on a surface of a same fin.

6. The test structure according to claim 1, further comprising:

at least one second conductive structure formed in the to-be-tested region,

wherein;

the at least one second conductive structure is in between a first gate structure and an adjacent second gate structure;

the at least one second conductive structure crosses over at least two fins; and

the at least one second conductive structure is on surfaces of source/drain regions in at least two fins.

7. The test structure according to claim 1, wherein the source/drain regions comprise:

stress layers doped with certain ions.

8. The test structure according to claim 7, wherein:

the stress layers are made of one of silicon and silicon germanium; and

doping ions are P-type ions.

9. The test structure according to claim 7, wherein:

the stress layers are made of one of silicon and silicon carbide; and

doping ions are N-type ions.

10. The test structure according to claim 1, further comprising:

a plurality of third conductive structures formed on portions of the at least one first gate structure and the plurality of second gate structures.

11. The test structure according to claim 1, further comprising:

a dielectric layer formed on surfaces of the insulation layer, the fins, the at least one first gate structure and the plurality of second gate structures; and

the plurality of first conductive structures are formed in the insulation layer, and penetrate through the dielectric layer.

12. The test structure according to claim 1, wherein:

the plurality of first conductive structures are formed on portions of side surfaces of the fins and portions of a surface of the insulation layer.

13. The test structure according to claim 1, wherein:

surfaces of a source region and a drain region at both sides of a second gate structure on a surface of at least one fin all have at least one first conductive structure.

14. The test structure according to claim 1, wherein the at least one first gate structure and the plurality of second gate structures comprise:

a gate dielectric layer formed on portions of side and top surfaces of the fins;

a gate electrode layer formed on the gate dielectric layer; and

sidewall spacers formed on side surfaces of the gate electrode layer and the gate dielectric layer.

15. The test structure according to claim 14, wherein:

the gate dielectric layer is made of a high dielectric constant (high-K) material; and

the gate electrode layer is made of one or more of metal and metal compound.

16. A method for forming a test structure, comprising:

providing a substrate having a to-be-tested region and a peripheral region;

forming at least one fin on the substrate in the to-be-tested region and at least one fin on the substrate in the peripheral region;

wherein;

the at least one fin in the to-be-tested region and the at least one fin in the peripheral region are parallel; and

two ends of the at least one fin in the to-be-tested region extends into the peripheral region,

forming an insulation layer covering portions of side surfaces of the fins over the substrate;

forming at least one first gate structure crossing over the at least one fin in the to-be-tested region and covering portions of side surfaces of the at least one fin in the to-be-tested region over the insulation layer;

forming a plurality of parallel second gate structures covering portions of side surfaces of the at least one fin in the peripheral region, crossing over the at least one fin in the peripheral region and being parallel to the at least one first gate structure over the insulation layer;

forming source/drain regions in portions of the fins between adjacent second gate structures and portions of the fins between the at least one first gate structure and adjacent second gate structures; and

forming a plurality of first conducive structures in the peripheral region,

wherein;

the plurality of first conductive structures are in between adjacent second gate structures,

the plurality of first conductive structures cross over at least two fins; and

the plurality of first conductive structures are on surfaces of source/drain regions of at least two fins.

17. The method according to claim 16, wherein forming the at least first gate structure and the plurality of second gate structures comprises:

forming at least one first dummy gate structure having a dummy gate layer, crossing over the at least one fin in the to-be-tested region, and covering portions of side and top surfaces of the at least one fin in the to-be-tested region over the substrate;

forming a plurality of parallel second dummy gate structures having a dummy gate layer, crossing over the at least one fin in the peripheral region, and covering portions of side and top surfaces of the at least one fin in the peripheral region and being parallel with the at least one first dummy gate structure over the substrate;

forming a first sub-dielectric layer exposing top surfaces of the dummy gate layer on surfaces of the insulation layer and the fins and side surfaces of the at least one first dummy gate structure and the at least one second dummy gate structure;

removing the dummy gate layer to form trenches in the first sub-dielectric layer;

forming a gate dielectric layer on inner surfaces of the trenches;

forming a gate layer on a surface of the gate dielectric layer by filling the trenches; and

planarizing the gate dielectric layer and the gate layer until a surface of the first sub-dielectric layer is exposed.

18. The method according to claim 17, wherein forming the plurality of first conductive structures comprises:

forming a second sub-dielectric layer on surfaces of the at least one first gate structure and the at least one second gate structure; and

forming the plurality of first conductive structures in portions of the first sub-dielectric layer and the second sub-dielectric layer between adjacent second gate structures and on surfaces of the source/drain regions.

19. A test method, comprising:

providing a test structure having a substrate having a to-be-tested region and a peripheral region surrounding the to-be-tested region, the to-be-tested region having at least one fin, the peripheral region having at least one fin, the at least one fin in the to-be-tested region being parallel to the at least one fin in the peripheral region, and two ends of the at least one fin in the to-be-tested region extending into the peripheral region;

an insulation layer, covering portions of side surfaces of the fins;

at least one first gate structure covering side and top surfaces of the at least one fin in the to-be-tested region;

a plurality of parallel second gate structures covering side and top surfaces of the at least one fin in the peripheral region, and the second gate structures being parallel to the first gate structure;

source/drain regions formed in portions of the at least one fin between adjacent second gate structures and portions of the at least one fin between the at least one first gate structure and adjacent second gate structures; and

a plurality of first conductive structures formed between adjacent second gate structures in the peripheral region, the plurality of first conductive structures crossing over at least two fins, and the plurality of first conductive structures being on surfaces of source/drain regions of at least two fins,

wherein;

a first gate structure and a source region at one side of the first gate structure and a corresponding drain region at another side of the first gate structure form a first transistor;

a second gate structure and a source region at one side of the second gate structure and a corresponding drain region at another side of the second gate structure form a second transistor;

the to-be-test region has at least one first transistor; and

the peripheral region has a plurality of second transistors,

turning on the at least one first transistor;

performing temperature tests on the plurality of second transistors with pre-determined time intervals to obtain temperatures of the fins under the second gate structures; and

obtaining correlations between the temperatures of the fins in the peripheral region and time.

20. The test method according to claim 19, wherein the temperature tests comprise:

testing saturated currents and gate voltages of the second transistors to obtain correlation curves of the saturated currents and the gate voltages of the second transistors;

obtaining slopes of the correlation curves of the saturated currents and the gate voltages of the second transistors; and

obtaining temperatures of the fins under the second gate structures according to the slopes of the correlation curves of the saturated currents and the gate voltages of the second transistors