MEMORY SYSTEM THAT SELECTS DATA TO BE TRANSMITTED FROM A DATA BUFFER THROUGH A PORT

• US 20170083248A1
• Filed: 03/07/2016
• Published: 03/23/2017
• Est. Priority Date: 09/22/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kikuchi, Takeshi, Okita, Kazuhito
• Granted Patent: US 10,747,445 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2213/0028 Serial attached SCSI [SAS]
• CPC Class Codes: G06F 2213/4004 Universal serial bus hub with a plurality of upstream ports
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory system includes a non-volatile memory, a data buffer in which data read out from the nonvolatile memory are stored prior to transmission to an initiator that is requesting the data, a port through which the initiator sends a request for the data and through which the data in the data buffer are transmitted to the initiator. When the port is connected to a first initiator at a time both first data requested by the first initiator and second data requested by a second initiator are stored in the data buffer and the second data become ready for transmission prior to the first data, the second data are transmitted through the port prior to the first data.

Claims

1. A memory system, comprising:

a nonvolatile memory;

a data buffer in which data read out from the nonvolatile memory are stored prior to transmission to an initiator that is requesting the data; and

a port through which the initiator sends a request for the data and through which the data in the data buffer are transmitted to the initiator, wherein

when the port is connected to a first initiator at a time both first data requested by the first initiator and second data requested by a second initiator are stored in the data buffer and the second data become ready for transmission prior to the first data, the second data are transmitted through the port prior to the first data.

2. The memory system according to claim 1, wherein

when the port is connected to the first initiator at a time both the first data and the second data are stored in the data buffer and the first data become ready for transmission prior to the second data, the first data are transmitted through the port prior to the second data.

3. The memory system according to claim 2, wherein

when the port is connected to the first initiator at a time third data requested by the first initiator are stored in the data buffer and become ready for transmission subsequent to the second data, the third data are transmitted through the port prior to the second data.

4. The memory system according to claim 1, wherein

when the port is connected to no initiator at a time both the first data and the second data are stored in the data buffer and the first data become ready for transmission prior to the second data, a connection request is transmitted through the port to the first initiator.

5. The memory system according to claim 4, wherein

when the port is connected to the first initiator in response to the connection request, the first data are transmitted through the port prior to the second data.

6. The memory system according to claim 1, wherein

the data become ready for transmission when the data read out from the nonvolatile memory start to be stored in the data buffer.

7. The memory system according to claim 1, wherein

the port is connected with an initiator through an expander.

8. The memory system according to claim 1, wherein

the port is configured to conform to Serial Attached SCSI (SAS) protocol.

9. The memory system according to claim 1, further comprising:

one or more additional ports; and

a counter configured to separately count for each of the ports the number of data units transmitted through said each of the ports, wherein

data requested through a port that has the lowest counted number are selected to be read out from the nonvolatile memory and stored in the data buffer next.

10. The memory system according to claim 1, further comprising:

a plurality of ports, including said port; and

a counter configured to separately count for each of the ports the number of data units stored in the data buffer for transmission through said each of the ports, wherein

data requested through a port that has the lowest counted number are selected to be read out from the nonvolatile memory and stored in the data buffer next.

11. A memory system, comprising:

a nonvolatile memory;

a data buffer in which data read out from the nonvolatile memory are stored prior to transmission to an initiator that is requesting the data; and

a port through which the initiator sends a request for the data and through which the data in the data buffer are transmitted to the initiator, wherein

when the port is connected to a first initiator at a time both first data requested by the first initiator and second data requested by a second initiator are stored in the data buffer and the second data become ready for transmission prior to the first data, a connection request is transmitted to the second initiator one or more times until connection to the second initiator is successfully established or until a maximum number of attempts or a maximum amount of time has been reached.

12. The memory system according to claim 11, wherein

when the connection to the second initiator is successfully established, the second data are transmitted through the port prior to the first data, and

when the connection to the second initiator is not successfully established, the first data are transmitted through the port prior to the second data.

13. The memory system according to claim 11, wherein

when the port is connected to the first initiator at a time both the first data and the second data are stored in the data buffer and the first data become ready for transmission prior to the second data, the first data are transmitted through the port prior to the second data.

14. The memory system according to claim 13, wherein

when the port is connected to the first initiator at a time third data requested by the first initiator are stored in the data buffer and become ready for transmission subsequent to the second data, the third data are transmitted through the port prior to the second data.

15. The memory system according to claim 11, wherein

when the port is connected to no initiator at a time both the first data and the second data are stored in the data buffer and the first data become ready for transmission prior to the second data, a connection request is transmitted through the port to the first initiator.

16. The memory system according to claim 11, further comprising:

one or more additional ports; and

a counter configured to separately count for each of the ports the number of data units transmitted through said each of the ports, wherein

data requested through a port that has the lowest counted number are selected to be read out from the nonvolatile memory and stored in the data buffer next.

17. The memory system according to claim 11, further comprising:

a plurality of ports, including said port; and

a counter configured to separately count for each of the ports the number of data units stored in the data buffer for transmission through said each of the ports, wherein

data requested through a port that has the lowest counted number are selected to be read out from the nonvolatile memory and stored in the data buffer next.

18. A memory system, comprising:

a nonvolatile memory;

a data buffer in which data read out from the nonvolatile memory are stored prior to transmission to an initiator that is requesting the data;

a plurality of ports; and

a first counter configured to separately count for each of the ports the number of data units transmitted through said each of the ports, wherein

in a first operational mode, data requested through a port that has the lowest counted number in the first counter are selected to be read out from the nonvolatile memory and stored in the data buffer next.

19. The memory system according to claim 18, further comprising:

a second counter configured to separately count for each of the ports the number of data units stored in the data buffer for transmission through said each of the ports, wherein

in a second operational mode, data requested through a port that has the lowest counted number in the second counter are selected to be read out from the nonvolatile memory and stored in the data buffer next.

20. The memory system according to claim 19, wherein

each of the ports is configured to conform to Serial Attached SCSI (SAS) protocol.