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CONFIGURING COARSE-GRAINED RECONFIGURABLE ARRAYS (CGRAs) FOR DATAFLOW INSTRUCTION BLOCK EXECUTION IN BLOCK-BASED DATAFLOW INSTRUCTION SET ARCHITECTURES (ISAs)

  • US 20170083313A1
  • Filed: 09/22/2015
  • Published: 03/23/2017
  • Est. Priority Date: 09/22/2015
  • Status: Abandoned Application
First Claim
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1. A coarse-grained reconfigurable array (CGRA) configuration circuit of a block-based dataflow instruction set architecture (ISA), comprising:

  • a CGRA comprising a plurality of tiles, each tile among of the plurality of tiles comprising a functional unit and a switch; and

    an instruction decoding circuit configured to;

    receive, from a block-based dataflow computer processor core, a dataflow instruction block comprising a plurality of dataflow instructions; and

    for each dataflow instruction of the plurality of dataflow instructions;

    map the dataflow instruction to a tile of the plurality of tiles of the CGRA;

    decode the dataflow instruction;

    generate a function control configuration for the functional unit of the mapped tile to correspond to a functionality of the dataflow instruction; and

    for each consumer instruction of the dataflow instruction, generate a switch control configuration of the switch of each of one or more path tiles of the plurality of tiles of the CGRA to route an output of the functional unit of the mapped tile to a destination tile of the plurality of tiles of the CGRA corresponding to the consumer instruction.

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