MEMORY SYNCHRONIZATION IN BLOCK-BASED PROCESSORS

• US 20170083331A1
• Filed: 03/16/2016
• Published: 03/23/2017
• Est. Priority Date: 09/19/2015
• Status: Abandoned Application

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Burger, Douglas C., Smith, Aaron L.
• Application Number:
  US15/072,031
• Publication Number:
  US 20170083331A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/36 Preventing errors by testing or debugging software
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Abstract

Apparatus and methods are disclosed for performing memory operations instructions in a block-based processor architecture. In certain examples of the disclosed technology, a block-based processor core coupled to memory includes a control unit configured to issue one or more memory operations encoded in an instruction block allocated to the core and to commit the core when execution of the instruction block is complete, a memory store queue configured to cache one or more operands for the one or more memory operations, where a result of performing the memory operations is not architecturally visible unless the instruction block is committed by the control unit, and a memory interface configured to store the cached operands in the memory responsive to the instruction block committing. In some examples, the block-based processor core supports memory synchronization using load linked and store conditional instructions.

Claims

1. An apparatus comprising one or more block-based processor cores coupled to a memory, at least one of the cores comprising:

a control unit configured to issue one or more memory operations encoded in an instruction block allocated to the at least one core and to commit the core when execution of the instruction block is complete;

a memory store queue configured to cache one or more operands for the one or more memory operations, wherein a result produced by performing the memory operations is not architecturally visible unless the instruction block is committed by the control unit; and

a memory interface configured to store the cached operands in the memory responsive to the instruction block committing.

2. The apparatus of claim 1, wherein at least one of the memory operations is a store conditional instruction.

3. The apparatus of claim 1, wherein at least one of the memory operations is an unconditional store instruction or a load linked instruction.

4. The apparatus of claim 1, wherein the control unit is further configured to:

observe a store operation performed by the memory interface to store the cached operands and generate a status indicator value indicating whether the store operation was successful.

5. The apparatus of claim 4, wherein the status indicator value is stored in a target specified by a store conditional instruction.

6. The apparatus of claim 1, wherein at least one of the cores is further configured to, if the memory interface cannot store the cached operand, then flush the instruction block.

7. The apparatus of claim 1, wherein the block-based processor cores are configured for multi-processor and/or multi-threaded operation.

8. The apparatus of claim 1, further comprising a load linked address register storing a memory address for a current synchronized memory operation and a load linked register storing data indicating whether a memory location associated with the memory address is currently linked to by a thread or process.

9. A method of operating a block-based processor to execute an instruction block using a memory unit coupled to the block-based processor, the method comprising:

executing a memory store instruction specified in the instruction block by storing one or more operands of the memory store instruction in a store queue of the block-based processor;

generating a status indicator value indicating whether a memory operation specified by the memory store instruction was successful; and

if the instruction block commits, attempting to perform a memory operation with the memory unit based on the operands stored in the store queue.

10. The method of claim 9, further comprising, if the memory operation is successful, then sending the status indicator value indicating success to a target operand specified by the memory store instruction.

11. The method of claim 9, further comprising, if the memory operation is not successful, then sending the status indicator value indicating failure to a target operand specified by the memory store instruction.

12. The method of claim 11, wherein the instruction block is a first instruction block, and wherein the method further comprises:

receiving the result data with a second instruction block via a global register and, based on the status indicator value indicating failure, causing the processor to re-execute the first instruction block.

13. The method of claim 9, wherein a result of attempting to perform the memory operation is not architecturally visible until the instruction block commits

14. The method of claim 9, further comprising:

after the executing the memory store instruction, executing one or more additional instructions specified in the instruction block; and

after the executing the one or more additional instructions, committing the instruction block, the committing including writing the operands stored in the store queue to the memory unit.

15. The method of claim 9, wherein the memory store instruction is a store conditional instruction, and wherein executing the store conditional instruction causes the processor to compare an input operand value to a value stored in a load linked address register, and if the values match, then perform the memory store operation.

16. The method of claim 9, wherein the memory store instruction is a store conditional instruction, and wherein executing the store conditional instruction causes the processor to evaluate a link value and based on the link value, then perform the memory store operation.

17. The method of claim 16, further comprising, prior to issuing the memory store instruction, executing a load linked instruction that causes the processor to:

read a data value from an address location in the memory unit;

store the address location in the load linked address register; and

set a value to indicate that the address location is linked.

18. One or more computer-readable storage media storing computer-readable instructions that when executed by a block-based processor, cause the processor to perform a method, the computer-readable instructions comprising:

instructions for analyzing source code and/or object code for an instruction block to identify one or more synchronized memory operations specified by the code; and

instructions for transforming the source code and/or object code into computer-executable code for the instruction block, the computer-executable code being executable by a block-based processor and including one or more instructions for performing the identified synchronized memory operations, wherein a result of the performing is not architecturally visible until the instruction block is committed by the block-based processor.

19. The one or more computer-readable storage media of claim 18, further comprising instructions for storing the computer-executable code in a computer-readable storage medium, wherein the stored instructions include at least one load linked instruction and at least one store conditional instruction.

20. The one or more computer-readable storage media of claim 18, wherein the instruction block is a first instruction block, and wherein the computer-readable instructions further comprise:

instructions for a subsequent instruction block including instructions for checking the result, and, if the result indicates a memory store operation did not complete, then re-executing the first instruction block or flushing the first instruction block.