HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER
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Abstract
A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.
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Citations
74 Claims
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1-50. -50. (canceled)
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51. A processor device comprising:
physical layer logic to; enter a loopback state of a state machine; generate, using a linear feedback shift register, a loopback pattern comprising a pseudo random bit sequence (PRBS); transmit the loopback pattern to another processor device over a physical connection, wherein an instance of the loopback pattern is to also be generated by the other processor device, and the loopback pattern is transmitted according to a first setting of transmitter parameters of the processor device; adjust the first setting of transmitter parameters of the processor device based on metrics generated based on a comparison by the other processor device of the loopback pattern received by the other processor and the instance of the loopback pattern generated by the other processor device, wherein adjusting the first setting of transmitter parameters results in a second setting of transmitter parameters of the processor device; transmit another instance of the loopback pattern to the other processor device according to the second setting of transmitter parameters of the processor device. - View Dependent Claims (52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62)
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63. An apparatus comprising:
a controller associated with a first processor to interface between the first processor to recognize a first instruction set and a second processor to recognize a second instruction set that is different from the first instruction set, the controller comprising protocol layer logic, link layer logic, and physical layer logic, the physical layer logic to; send a supersequence to the second processor over an interconnect, wherein the supersequence indicates a loopback state, transmitter adaptation is to be performed in the loopback state, the supersequence comprises a series of training sequences, and one or more of the training sequences in the series comprise; a training sequence type field to indicate the loopback state, and a loopback master bit to indicate that the first processor is to serve as master in the transmitter adaptation; generate, using a linear feedback shift register, a loopback pattern comprising a pseudo random bit sequence (PRBS); transmit the loopback pattern to the second processor over the interconnect, wherein the loopback pattern is to be sent according to first transmitter parameter settings; examine a metric generated at the second processor based on receipt of the loopback pattern at the second processor; identify second transmitter parameter settings based on the metric; and transmit the loopback pattern to the second processor over the interconnect, wherein the loopback pattern is to be sent according to second transmitter parameter settings. - View Dependent Claims (64, 65, 66, 67, 68)
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69. A method comprising:
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sending a supersequence to the second processor over an interconnect, wherein the supersequence indicates a loopback state, transmitter adaptation is to be performed in the loopback state, the supersequence comprises a series of training sequences, and one or more of the training sequences in the series comprise; a training sequence type field to indicate the loopback state, and a loopback master bit to indicate that the first processor is to serve as master in the transmitter adaptation; generating, using a linear feedback shift register, a loopback pattern comprising a pseudo random bit sequence (PRBS); transmitting the loopback pattern to the second processor over the interconnect, wherein the loopback pattern is to be sent according to first transmitter parameter settings; examining a metric generated at the second processor based on receipt of the loopback pattern at the second processor; identifying second transmitter parameter settings based on the metric; and transmitting the loopback pattern to the second processor over the interconnect, wherein the loopback pattern is to be sent according to second transmitter parameter settings.
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70. A system comprising:
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a first processor; and a second processor coupled to the first processor device by a link, wherein the second processor device comprises physical layer logic to; enter a loopback state of a state machine; generate, using a linear feedback shift register, a first instance of a loopback pattern comprising a pseudo random bit sequence (PRBS); receive a second instance of the loopback pattern from the first processor over the link; compare the second instance with the first instance of the loopback pattern; generate a metric based on comparison of the second instance with the first instance of the loopback pattern, wherein the metric is to be used to adapt transmitter parameter settings of the first processor. - View Dependent Claims (71, 72, 73)
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74. A system comprising:
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means for sending a supersequence to the second processor over an interconnect, wherein the supersequence indicates a loopback state, transmitter adaptation is to be performed in the loopback state, the supersequence comprises a series of training sequences, and one or more of the training sequences in the series comprise; a training sequence type field to indicate the loopback state, and a loopback master bit to indicate that the first processor is to serve as master in the transmitter adaptation; means for generating, using a linear feedback shift register, a loopback pattern comprising a pseudo random bit sequence (PRBS); means for transmitting the loopback pattern to the second processor over the interconnect, wherein the loopback pattern is to be sent according to first transmitter parameter settings; means for examining a metric generated at the second processor based on receipt of the loopback pattern at the second processor; means for identifying second transmitter parameter settings based on the metric; and means for transmitting the loopback pattern to the second processor over the interconnect, wherein the loopback pattern is to be sent according to second transmitter parameter settings.
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Specification