HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER

• US 20170083476A1
• Filed: 06/27/2016
• Published: 03/23/2017
• Est. Priority Date: 10/22/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Iyer, Venkatraman, Jue, Darren S., Shah, Rahul, Kumar, Arvind
• Granted Patent: US 9,892,086 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 13/22 using successive scanning, e.g. polling G06F13/24 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 13/4273 using a clocked protocol
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 13/4286 using a handshaking protocol, e.g. RS232C link
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/2542 Non-uniform memory access [NUMA] architecture
• CPC Class Codes: G06F 2212/622 State-only directory, i.e. not recording identity of sharing or owning nodes
• CPC Class Codes: G06F 8/71 Version control security arrangements therefor G06F21/57; Configuration management
• CPC Class Codes: G06F 8/73 : Program documentation
• CPC Class Codes: G06F 8/77 : Software metrics
• CPC Class Codes: G06F 9/30145 : Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/44505 : Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: G06F 9/466 : Transaction processing
• CPC Class Codes: H04L 12/4641 : Virtual LANs, VLANs, e.g. virtual private networks [VPN] LAN interconnection over a bridge based backbone H04L12/462; encapsulation techniques H04L12/4633; routing of packets H04L45/00; packet switches H04L49/00; virtual private networks for security H04L63/0272
• CPC Class Codes: H04L 45/74 : Address processing for routing
• CPC Class Codes: H04L 49/15 : Interconnection of switching modules
• CPC Class Codes: H04L 9/0662 : with particular pseudorandom sequence generator
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/00 : Reducing energy consumption in communication networks

Abstract

A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.

Claims

1-50. -50. (canceled)

51. A processor device comprising:

physical layer logic to;

enter a loopback state of a state machine;

generate, using a linear feedback shift register, a loopback pattern comprising a pseudo random bit sequence (PRBS);

transmit the loopback pattern to another processor device over a physical connection, wherein an instance of the loopback pattern is to also be generated by the other processor device, and the loopback pattern is transmitted according to a first setting of transmitter parameters of the processor device;

adjust the first setting of transmitter parameters of the processor device based on metrics generated based on a comparison by the other processor device of the loopback pattern received by the other processor and the instance of the loopback pattern generated by the other processor device, wherein adjusting the first setting of transmitter parameters results in a second setting of transmitter parameters of the processor device;

transmit another instance of the loopback pattern to the other processor device according to the second setting of transmitter parameters of the processor device.

52. The processor device of claim 51, wherein the physical layer logic is further to:

receive the instance of the loopback pattern generated by the other processor device;

compare the received instance of the loopback pattern with the loopback pattern generated locally at the processor device; and

determine a particular metric based on comparison of the received instance of the loopback pattern with the loopback pattern generated locally at the processor device, wherein transmitter parameters of the other processor device are to be adjusted based on the particular metric.

53. The processor device of claim 51, wherein the loopback pattern comprises an electrical ordered set (EOS).

54. The processor device of claim 53, wherein the loopback pattern further comprises a series of training sequences.

55. The processor device of claim 54, wherein the series of training sequences comprises a predefined number of training sequences.

56. The processor device of claim 55, wherein the predefined number of training sequences comprise thirty training sequences.

57. The processor device of claim 54, wherein the loopback pattern comprises a repeating pattern of the EOS and series of training sequences.

58. The processor device of claim 53, wherein the EOS comprises an electrical idle exit ordered set (EIEOS).

59. The processor device of claim 58, wherein:

the EIEOS comprises a 16 byte ordered set,

bytes 0, 2, 4, 6, 8, 10, 12, and 14 of the EIEOS comprise a value 8′

h00, and

bytes 1, 3, 5, 7, 9, 11, 13, and 15 of the EIEOS comprise a value 8′

hFF.

60. The processor device of claim 51, wherein the metrics are to be received over a backchannel.

61. The processor device of claim 60, wherein the backchannel comprises a software-implemented backchannel.

62. The processor device of claim 61, wherein the software-implemented backchannel utilizes a slow mode of an embedded clock for the physical connection.

63. An apparatus comprising:

a controller associated with a first processor to interface between the first processor to recognize a first instruction set and a second processor to recognize a second instruction set that is different from the first instruction set, the controller comprising protocol layer logic, link layer logic, and physical layer logic, the physical layer logic to;

send a supersequence to the second processor over an interconnect, wherein the supersequence indicates a loopback state, transmitter adaptation is to be performed in the loopback state, the supersequence comprises a series of training sequences, and one or more of the training sequences in the series comprise;

a training sequence type field to indicate the loopback state, and

a loopback master bit to indicate that the first processor is to serve as master in the transmitter adaptation;

generate, using a linear feedback shift register, a loopback pattern comprising a pseudo random bit sequence (PRBS);

transmit the loopback pattern to the second processor over the interconnect, wherein the loopback pattern is to be sent according to first transmitter parameter settings;

examine a metric generated at the second processor based on receipt of the loopback pattern at the second processor;

identify second transmitter parameter settings based on the metric; and

transmit the loopback pattern to the second processor over the interconnect, wherein the loopback pattern is to be sent according to second transmitter parameter settings.

64. The apparatus of claim 63, wherein the PRBS is a 23 bit PRBS.

65. The apparatus of claim 64, wherein the PRBS is to be generated using a Fibonacci linear feedback shift register (LFSR).

66. The apparatus of claim 63, wherein the PRBS comprises a control supersequence and at least a portion of the supersequence is scrambled using the PRBS.

67. The apparatus of claim 66, wherein the supersequence comprises a repeating sequence including an electric idle exit ordered set (EIEOS), wherein the sequence is to be repeated according to a particular predefined frequency.

68. The apparatus of claim 67, wherein the sequence includes a defined number of training sequences following the EIEOS.

69. A method comprising:

sending a supersequence to the second processor over an interconnect, wherein the supersequence indicates a loopback state, transmitter adaptation is to be performed in the loopback state, the supersequence comprises a series of training sequences, and one or more of the training sequences in the series comprise;

a training sequence type field to indicate the loopback state, and

a loopback master bit to indicate that the first processor is to serve as master in the transmitter adaptation;

generating, using a linear feedback shift register, a loopback pattern comprising a pseudo random bit sequence (PRBS);

transmitting the loopback pattern to the second processor over the interconnect, wherein the loopback pattern is to be sent according to first transmitter parameter settings;

examining a metric generated at the second processor based on receipt of the loopback pattern at the second processor;

identifying second transmitter parameter settings based on the metric; and

transmitting the loopback pattern to the second processor over the interconnect, wherein the loopback pattern is to be sent according to second transmitter parameter settings.

70. A system comprising:

a first processor; and

a second processor coupled to the first processor device by a link, wherein the second processor device comprises physical layer logic to;

enter a loopback state of a state machine;

generate, using a linear feedback shift register, a first instance of a loopback pattern comprising a pseudo random bit sequence (PRBS);

receive a second instance of the loopback pattern from the first processor over the link;

compare the second instance with the first instance of the loopback pattern;

generate a metric based on comparison of the second instance with the first instance of the loopback pattern, wherein the metric is to be used to adapt transmitter parameter settings of the first processor.

71. The system of claim 70, wherein the first processor comprises physical layer logic to generate the PRBS.

72. The system of claim 71, wherein the physical layer logic of the second processor is further to send the first instance of the loopback pattern to the first processor.

73. The system of claim 72, wherein the physical layer logic of the first processor is further to:

receive the first instance of the loopback pattern from the second processor over the link;

compare the first instance with the second instance of the loopback pattern;

generate a metric based on comparison of the first instance with the second instance of the loopback pattern, wherein the metric is to be used to adapt transmitter parameter settings of the second processor.

74. A system comprising:

means for sending a supersequence to the second processor over an interconnect, wherein the supersequence indicates a loopback state, transmitter adaptation is to be performed in the loopback state, the supersequence comprises a series of training sequences, and one or more of the training sequences in the series comprise;

a training sequence type field to indicate the loopback state, and

a loopback master bit to indicate that the first processor is to serve as master in the transmitter adaptation;

means for generating, using a linear feedback shift register, a loopback pattern comprising a pseudo random bit sequence (PRBS);

means for transmitting the loopback pattern to the second processor over the interconnect, wherein the loopback pattern is to be sent according to first transmitter parameter settings;

means for examining a metric generated at the second processor based on receipt of the loopback pattern at the second processor;

means for identifying second transmitter parameter settings based on the metric; and

means for transmitting the loopback pattern to the second processor over the interconnect, wherein the loopback pattern is to be sent according to second transmitter parameter settings.