SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME

• US 20170084519A1
• Filed: 09/22/2015
• Published: 03/23/2017
• Est. Priority Date: 09/22/2015
• Status: Abandoned Application

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Speight, Thomas C., Hooper, Stephen R.
• Application Number:
  US14/861,543
• Publication Number:
  US 20170084519A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49861 Lead-frames fixed on or encapsulated in insulating substrates H01L23/4985, H01L23/49805 take precedence
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

A semiconductor die is electrically connected to the leads of a flagless lead frame and is fully encapsulated by encapsulant to form a semiconductor package. A method of manufacturing the semiconductor package entails encapsulating a flagless lead frame with a first encapsulant such that a top surface of the leads of the flagless lead frame are exposed from the first encapsulant. A semiconductor die is mounted directly to the first encapsulant located in a central region of the lead frame. Electrically conductive interconnects are formed between die pads on the semiconductor die and the top surface of respective leads of the lead frame. The semiconductor die, conductive interconnects, and top surface of the leads is encapsulated with a second encapsulant so that the semiconductor die is sandwiched between the first and second encapsulants, thus isolating the semiconductor die from package stresses.

Claims

1. A method for manufacturing a semiconductor package comprising:

providing a lead frame, said lead frame being formed from an electrically conductive sheet having a plurality of leads extending from a lead frame boundary towards a central region of said lead frame;

encapsulating said lead frame with a first encapsulant such that a top surface of each of said leads is exposed from said first encapsulant;

mounting a semiconductor die on said first encapsulant located in said central region of said lead frame;

forming electrically conductive interconnects between die pads on said semiconductor die and said top surface of respective ones of said plurality of leads; and

encapsulating said semiconductor die, said conductive interconnects, and said top surface of said leads with a second encapsulant.

2. The method of claim 1 wherein said lead frame exhibits a first height, and said encapsulating said lead frame in said first encapsulant forms a molded structure having a second height that is approximately equivalent to said first height.

3. The method of claim 1 wherein said encapsulating said lead frame in said first encapsulant includes exposing a bottom surface of said leads from said first encapsulant.

4. The method of claim 1 wherein said encapsulating said lead frame in said first encapsulant is performed prior to said operations of mounting, forming, and encapsulating with said second encapsulant.

5. The method of claim 1 wherein said lead frame is a flagless lead frame, and said mounting operation includes directly coupling said semiconductor die to said first encapsulant in said central region.

6. The method of claim 1 wherein said semiconductor die has a connection pad surface with said die pads thereon and a second surface on an opposite side of said semiconductor die from said connection pad surface, and said mounting operation couples said second surface of said semiconductor die to said first encapsulant in said central region.

7. The method of claim 6 wherein said second surface of said semiconductor die is approximately coplanar with said top surface of said leads following said mounting operation.

8. The method of claim 1 further comprising separating said leads from said lead frame boundary following both of said encapsulating operations.

9. The method of claim 1 wherein said semiconductor die is sandwiched between said first encapsulant and said second encapsulant following both of said encapsulating operations.

10. A method for manufacturing a plurality of semiconductor packages comprising:

providing an electrically conductive sheet of flagless lead frames, each of said flagless lead frames having a plurality of leads extending from a lead frame boundary towards a central region of said lead frame;

encapsulating said electrically conductive sheet of flagless lead frames with a first encapsulant such that a top surface of each of said leads is exposed from said first encapsulant;

mounting semiconductor dies on said first encapsulant located in each said central region of said each of said flagless lead frames by directly coupling said semiconductor dies to said first encapsulant;

forming electrically conductive interconnects between die pads on said semiconductor dies and said top surface of respective ones of said plurality of leads;

encapsulating said semiconductor dies, said conductive interconnects, and said top surface of said leads with a second encapsulant to form a composite structure; and

separating said composite structure into said plurality of semiconductor packages following both of said encapsulating operations, each of said semiconductor dies being sandwiched between a portion of said first encapsulant and a portion of said second encapsulant.

11. The method of claim 10 wherein said electrically conductive sheet of flagless lead frames exhibits a first height, and said encapsulating said electrically conductive sheet in said first encapsulant forms a molded structure having a second height that is approximately equivalent to said first height.

12. The method of claim 10 wherein said encapsulating said electrically conductive sheet in said first encapsulant is performed prior to said operations of mounting, forming, and encapsulating with said second encapsulant.

13. The method of claim 10 wherein each of said semiconductor dies has a connection pad surface with said die pads thereon and a second surface on an opposite side of said semiconductor die from said connection pad surface, and said mounting operation couples said second surface of said semiconductor die directly to said first encapsulant in said central region.

14. The method of claim 13 wherein said second surface of said each of said semiconductor dies is approximately coplanar with said top surface of said leads following said mounting operation.

15. A semiconductor package comprising

a lead frame embedded in a first encapsulant, said lead frame being formed from an electrically conductive sheet having a plurality of leads extending from a lead frame boundary towards a central region of said lead frame, wherein a top surface of each of said leads is exposed from said first encapsulant;

a semiconductor die in direct contact with said first encapsulant located in said central region of said lead frame;

conductive interconnects electrically connected between die pads on said semiconductor die and said top surface of respective ones of said plurality of leads; and

a second encapsulant covering said semiconductor die, said conductive interconnects, and said top surface of said leads.

16. The semiconductor package of claim 15 wherein said lead frame exhibits a first height, and said lead frame embedded in said first encapsulant forms a molded structure having a second height that is approximately equivalent to said first height.

17. The semiconductor package of claim 15 wherein a bottom surface of said leads is exposed from said first encapsulant.

18. The semiconductor package of claim 15 wherein said semiconductor die has a connection pad surface with said die pads thereon and a second surface on an opposite side of said semiconductor die from said connection pad surface, said second surface of said semiconductor die being coupled to said first encapsulant in said central region.

19. The semiconductor package of claim 18 wherein said second surface of said semiconductor die is approximately coplanar with said top surface of said leads.

20. The method of claim 18 wherein said semiconductor die is sandwiched between said first encapsulant and said second encapsulant.