Semiconductor Devices Including FINFET Structures with Increased Gate Surface

• US 20170084616A1
• Filed: 07/19/2016
• Published: 03/23/2017
• Est. Priority Date: 09/18/2015
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Ki-Il, YOU, JUNG-GUN, PARK, Gi-gwan
• Application Number:
  US15/213,533
• Publication Number:
  US 20170084616A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A semiconductor device can include a field insulating film on a substrate and a fin-type pattern of a particular material, on the substrate, having a first sidewall and an opposing second sidewall. The fin-type pattern can include a first portion of the fin-type pattern that protrudes from an upper surface of the field insulating film and a second portion of the fin-type pattern disposed on the first portion. A third portion of the fin-type pattern can be disposed on the second portion where the third portion can be capped by a top rounded surface of the fin-type pattern and the first sidewall can have an undulated profile that spans the first, second and third portions.

Claims

1. A semiconductor device, comprising:

a first fin-type pattern on a substrate and having a first sidewall and an opposing second sidewall; and

a field insulating film on the substrate and surrounding a portion of the first sidewall of the first fin-type pattern and a portion of the second sidewall of the first fin-type pattern,

wherein the first fin-type pattern includes a lower portion surrounded by the field insulating film, an upper portion protruding upward beyond an upper surface of the field insulating film, and a boundary line is defined between the upper portion of the first fin-type pattern and the lower portion of the first fin-type pattern where the upper surface of the field insulating film meets the first fin-type pattern,

the upper portion of the first fin-type pattern and the lower portion of the first fin-type pattern include a same material,

the first sidewall of the first fin-type pattern includes a first point, a second point, and a third point positioned in a sequential order from an upper surface of the substrate,

a width across the first fin-type pattern at the second point is greater than a width across the first fin-type pattern at the first point and a width across the first fin-type pattern at the third point, and

the width across the first fin-type pattern at the second point is less than a length of the boundary line.

2. The semiconductor device of claim 1, wherein the upper portion of the first fin-type pattern includes the first to third points.

3. The semiconductor device of claim 1, wherein the first fin-type pattern includes a first portion at which a width across the first fin-type pattern increases as a distance from the upper surface of the substrate increases, and a second portion at which the width across the first fin-type pattern decreases as the distance from the upper surface of the substrate increases, and

the second point is positioned at a boundary between the first portion of the first fin-type pattern and the second portion of the second fin-type pattern.

4. The semiconductor device of claim 3, wherein the second point is positioned farther from the upper surface of the substrate than the boundary line.

5. The semiconductor device of claim 1, wherein a fin center line of the first fin-type pattern is defined to be orthogonal to the boundary line, and to meet an uppermost portion of the upper portion of the first fin-type pattern, and

a width across the first fin-type pattern from the fin center line to the first sidewall at the second point is greater than a width across the first fin-type pattern from the fin center line to the first sidewall at the first point, and greater than a width across the first fin-type pattern from the fin center line to the first sidewall at the third point.

6. The semiconductor device of claim 5, wherein a width across the first fin-type pattern from the fin center line to the second sidewall at the second point is greater than a width across the first fin-type pattern from the fin center line to the second sidewall at the first point, and greater than a width across the first fin-type pattern from the fin center line to the second sidewall at the third point.

7. The semiconductor device of claim 5, wherein a width across the first fin-type pattern from the fin center line to the second sidewall at the second point is less than a width across the first fin-type pattern from the fin center line to the second sidewall at the first point, and

the width across the first fin-type pattern from the fin center line to the second sidewall at the second point is greater than a width across the first fin-type pattern from the fin center line to the second sidewall at the third point.

9. The semiconductor device of claim 7, wherein a width across the first fin-type pattern from the fin center line to the second sidewall decreases as a distance from the upper surface of the substrate increases.

14. The semiconductor device of claim 1, further comprising a gate electrode on the field insulating film and crossing-over the first fin-type pattern.

8. (canceled)

10-13. -13. (canceled)

15. A semiconductor device, comprising:

a fin-type pattern on a substrate and including a first sidewall and a second sidewall; and

a field insulating film on the substrate and surrounding a portion of the first sidewall of the fin-type pattern and a portion of the second sidewall of the fin-type pattern,

wherein the fin-type pattern includes a lower portion surrounded by the field insulating film, and an upper portion protruding upward beyond an upper surface of the field insulating film,

the upper portion of the fin-type pattern and the lower portion of the fin-type pattern include a same material,

the upper portion of the fin-type pattern includes, on an upper surface of the field insulating film, a first portion at which a slope of the first sidewall makes an acute angle relative to an upper surface of the substrate, a second portion at which the slope of the first sidewall of the fin-type pattern makes an obtuse angle relative to the upper surface of the substrate, and a third portion at which the slope of the first sidewall of the fin-type pattern makes an acute angle relative to the upper surface of the substrate, and

the first to third portions are positioned in a sequential order relative to the upper surface of the substrate where changes from a first slope to a second slope to a third slope are provided by smooth transitions in a profile of the first sidewall.

16. The semiconductor device of claim 15, wherein the first sidewall has a slope at an acute angle relative to the upper surface of the substrate, then a slope at an obtuse angle relative to the upper surface of the substrate, and then a slope at an acute angle again relative to the upper surface of the substrate, as a distance along the first sidewall from the upper surface of the field insulating film increases.

17. The semiconductor device of claim 16, wherein the second sidewall pattern has a slope at an acute angle relative to the upper surface of the substrate, then a slope at an obtuse angle relative to the upper surface of the substrate, and then a slope at an acute angle again relative to the upper surface of the substrate, as a distance along the second sidewall from the upper surface of the field insulating film increases.

18. The semiconductor device of claim 16, wherein, beyond the upper surface of the field insulating film, the second sidewall has a slope at an acute angle relative to the upper surface of the substrate or a slope at a right angle relative to the upper surface of the substrate.

19. (canceled)

20. A semiconductor device, comprising:

a first fin-type pattern in a first region of a substrate and including first and second opposing sidewalls;

a second fin-type pattern in a second region of the substrate and including third and fourth opposing sidewalls; and

a field insulating film on the substrate and surrounding a portion of the first sidewall, a portion of a second sidewall, a portion of a third sidewall, and a portion of a fourth sidewall,

wherein the first fin-type pattern includes a lower portion surrounded by the field insulating film, an upper portion protruding upward beyond an upper surface of the field insulating film, and a boundary line defined to extend across the first fin-type pattern between the upper portion of the first fin-type pattern and the lower portion of the first fin-type pattern,

the first sidewall includes a first point, a second point, and a third point positioned in a sequential order relative to an upper surface of the substrate,

a width across the first fin-type pattern at the second point is greater than a width across the first fin-type pattern at the first point and greater than a width across the first fin-type pattern at the third point, and

the third sidewall and the fourth sidewall each have a slope at an acute angle relative to the upper surface of the substrate or a slope at a right angle relative to the upper surface of the substrate, as a distance from the upper surface of the substrate increases.

21. The semiconductor device of claim 20, wherein the upper portion of the first fin-type pattern and the lower portion of the first fin-type pattern, and the second fin-type pattern include a same material.

24. The semiconductor device of claim 20, wherein the first fin-type pattern includes

a first portion at which a width across the first fin-type pattern increases as the distance from the upper surface of the substrate increases, and a second portion at which the width across the first fin-type pattern decreases as the distance from the upper surface of the substrate increases, and

the second point is positioned at a boundary between the first portion of the first fin-type pattern and the second fin-type pattern.

25. The semiconductor device of claim 20, wherein the first sidewall has a slope at an acute angle relative to the upper surface of the substrate, then a slope at an obtuse angle relative to the upper surface of the substrate, and then a slope at an acute angle again relative to the upper surface of the substrate, as the distance from the upper surface of the field insulating film increases.

26. The semiconductor device of claim 20, wherein the first fin-type pattern is defined by a first trench in the substrate of a first depth, the second fin-type pattern is defined by a second trench in the substrate of a second depth, and

the second fin-type pattern is positioned in an active region defined by a third trench in the substrate of a third depth that is deeper than the second depth.

28. The semiconductor device of claim 20, further comprising:

a third fin-type pattern and a fourth fin-type pattern in the first region where the first fin-type pattern is located therebetween; and

a fifth fin-type pattern and a sixth fin-type pattern in the second region, where the second fin-type pattern is located therebetween,

wherein a distance between the second fin-type pattern and the fifth fin-type pattern is about equal to a distance between the second fin-type pattern and the sixth fin-type pattern, and

a distance between the first fin-type pattern and the third fin-type pattern is different from the distance between the second fin-type pattern and the fifth fin-type pattern.

32. The semiconductor device of claim 20, wherein the first region is a SRAM region, and the second region is a logic region.

22-23. -23. (canceled)

27. (canceled)

29-31. -31. (canceled)

33-51. -51. (canceled)