ARRAY SUBSTRATE AND DISPLAY DEVICE AND METHOD FOR MAKING THE ARRAY SUBSTRATE

• US 20170084641A1
• Filed: 06/30/2016
• Published: 03/23/2017
• Est. Priority Date: 09/18/2015
• Status: Abandoned Application

• Current Assignee: Hon Hai Precision Industry Co., Ltd.
• Original Assignee: Hon Hai Precision Industry Co., Ltd.
• Inventors: Lin, Hsin-Hua, KAO, YI-CHUN
• Application Number:
  US15/198,116
• Publication Number:
  US 20170084641A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1233 with different thicknesses of the active layer in different devices
• CPC Class Codes: H01L 27/1237 with a different composition, shape, layout or thickness of the gate insulator in different devices
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

An array substrate includes a substrate, and a first TFT and a second TFT on the substrate. The second TFT is a low-temperature poly silicon TFT. The first TFT includes a buffer layer, a gate, a gate insulator layer, and a metal oxide semiconductor layer stacked on the substrate in that order. A source electrode and a drain electrode are separately positioned on the gate insulator layer and coupled to the metal oxide semiconductor layer of the first TFT. The metal oxide semiconductor layer partially covers the source electrode and the drain electrode.

Claims

1. An array substrate comprising:

a substrate;

a first TFT on the substrate, the first TFT being a metal oxide TFT; and

a second TFT on the substrate, the second TFT being a low-temperature poly silicon TFT, the second TFT comprising a poly-silicon semiconductor layer, a buffer layer, a gate, and a gate insulator layer stacked on the substrate in that order, and a source electrode and a drain electrode passing through both the buffer layer and the gate insulator layer and coupled to the metal oxide semiconductor layer of the second TFT;

wherein the first TFT comprises a buffer layer, a gate, a gate insulator layer and a metal oxide semiconductor layer stacked on the substrate in that order, and a source electrode and a drain electrode separately positioned on the gate insulator layer and coupled to the metal oxide semiconductor layer of the first TFT;

the metal oxide semiconductor layer partially covers the source electrode and the drain electrode of the first TFT.

2. The array substrate of claim 1, wherein the buffer layer of the first TFT and the buffer layer of the second TFT are defined by a single layer and are simultaneously formed;

the gate insulator layer of the first TFT and the gate insulator layer of the second TFT are defined by a single layer and are simultaneously formed.

3. The array substrate of claim 2, wherein the gate insulator layer of the first TFT comprises a first gate insulator layer formed on the buffer layer of the first TFT and a second gate insulator layer formed on the first gate insulator layer of the first TFT;

and the gate insulator layers of the second TFT comprises a first gate insulator layer formed on the buffer layer of the second TFT and a second gate insulator layer formed on the first gate insulator layer of the second TFT.

4. The array substrate of claim 3, wherein the first gate insulator layers of the first TFT and the second TFT are made of silicon oxide;

and the second gate insulator layers of the first TFT and the second TFT are made of silicon nitride.

5. The array substrate of claim 1, further comprising a planar layer covering the first TFT and the second TFT, a common electrode on the planar layer, and a pixel electrode electrically coupled to the first TFT.

6. An array substrate comprising:

a substrate;

a switch TFT on the substrate, the switch TFT being a metal oxide TFT;

a driving TFT on the substrate, the driving TFT being a metal oxide TFT; and

a poly silicon TFT on the substrate, the poly silicon TFT comprising a poly-silicon semiconductor layer, a buffer layer, a gate, and a gate insulator layer stacked on the substrate in that order, and a source electrode and a drain electrode passing through both the buffer layer and the gate insulator layer and coupled to the metal oxide semiconductor layer of the second TFT,

wherein the switch TFT comprises a buffer layer, a gate, a gate insulator layer and a metal oxide semiconductor layer stacked on the substrate in that order, and a source electrode and a drain electrode separately positioned on the gate insulator layer and coupled to the metal oxide semiconductor layer of the switch TFT;

the metal oxide semiconductor layer of the switch TFT covers the source electrode and the drain electrode of the switch TFT; and

wherein the driving TFT comprises a buffer layer, a gate, a gate insulator layer and a metal oxide semiconductor layer stacked on the substrate in that order, and a source electrode and a drain electrode separately positioned on the gate insulator layer and coupled to the metal oxide semiconductor layer of the driving TFT;

the metal oxide semiconductor layer of the driving TFT covers the source electrode and the drain electrode of the driving TFT.

7. The array substrate of claim 6, wherein the buffer layers of the poly silicon TFT, the switch TFT, and the driving TFT are defined by a single layer and are simultaneously formed;

and

the gate insulator layers of the poly silicon TFT, the switch TFT, and the driving TFT are defined by a single layer and are simultaneously formed.

8. The array substrate of claim 6, wherein the gate insulator layer of the poly silicon TFT comprises a first gate insulator layer formed on the buffer layer of the poly silicon TFT and a second gate insulator layer formed on the first gate insulator layer;

the gate insulator layer of the switch TFT comprises a first gate insulator layer formed on the buffer layer of the switch TFT and a second gate insulator layer formed on the first gate insulator layer; and

the gate insulator layer of the driving TFT comprises a first gate insulator layer formed on the buffer layer of the driving TFT and a second gate insulator layer formed on the first gate insulator layer.

9. The array substrate of claim 8, wherein the first gate insulator layers of the poly silicon TFT, the switch TFT, and the driving TFT are made of the silicon oxide;

and the second gate insulator layers of the poly silicon TFT, the switch TFT, and the driving TFT are made of silicon nitride.

10. The array substrate of claim 6, wherein the array substrate further comprises a planar layer covering the switch TFT, the driving TFT, and the poly silicon TFT, a lighting emitting material layer on the planar layer, a cathode on the planar layer, a dielectric layer on the planar layer, and an anode on the planar layer and electrically coupled to the driving TFT.

11. A display device comprising:

an array substrate comprising;

a substrate;

a first TFT on the substrate, the first TFT being a metal oxide TFT; and

a second TFT on the substrate, the second TFT being a low-temperature poly silicon TFT, the second TFT comprising a poly-silicon semiconductor layer, a buffer layer, a gate, and a gate insulator layer stacked on the substrate in that order, and a source electrode and a drain electrode passing through both the buffer layer and the gate insulator layer and coupled to the metal oxide semiconductor layer of the second TFT;

wherein the first TFT comprises a buffer layer, a gate, a gate insulator layer and a metal oxide semiconductor layer stacked on the substrate in that order, and a source electrode and a drain electrode separately positioned on the gate insulator layer and coupled to the metal oxide semiconductor layer of the first TFT;

the metal oxide semiconductor layer partially covers the source electrode and the drain electrode.

12. The display device of claim 11, wherein the buffer layer of the first TFT and the buffer layer of the second TFT are defined by a single layer and are simultaneously formed;

the gate insulator layer of the first TFT and the gate insulator layer of the second TFT are defined by a single layer and are simultaneously formed.

13. The display device of claim 12, wherein the gate insulator layer of the first TFT comprises a first gate insulator layer formed on the buffer layer of the first TFT and a second gate insulator layer formed on the first gate insulator layer of the first TFT;

and the gate insulator layers of the second TFT comprises a first gate insulator layer formed on the buffer layer of the second TFT and a second gate insulator layer formed on the first gate insulator layer of the second TFT.

14. The display device of claim 13, wherein the first gate insulator layers of the first TFT and the second TFT are made of the silicon oxide;

and the second gate insulator layers of the first TFT and the second TFT are made of silicon nitride.

15. The display device of claim 11, wherein the array substrate further comprises a planar layer covering the first TFT and the second TFT, a common electrode on the planar layer, and a pixel electrode electrically coupled to the first TFT.

16. A method for making an array substrate comprising:

forming a poly-silicon semiconductor layer on a substrate;

forming a buffer layer on the poly-silicon semiconductor layer and the substrate;

depositing a first metal layer and patterning the first metal layer to form a first gate electrode and a second gate electrode, the first gate electrode corresponding to the poly-silicon semiconductor layer;

forming a gate insulator layer covering the first gate electrode and the second gate electrode;

defining a first hole and a second hole passing through the buffer layer and the gate insulator layer to expose the poly-silicon semiconductor layer;

depositing a second metal layer on the gate insulator layer and patterning the second metal layer to form a first source electrode in the first hole and a first drain electrode in the second through hole, a second source electrode and a second drain electrode on the gate insulator layer; and

depositing a metal oxide layer on the gate insulator layer and patterning the metal oxide layer to form a metal oxide semiconductor layer coupled to the second source electrode and the second drain electrode.

17. The method of claim 16, wherein the method further comprises forming a planar layer to cover the gate insulator layer, the metal oxide semiconductor layer, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode.

18. The method of claim 17, wherein the method further comprises forming an anode on the planar layer which is electrically coupled to the second drain electrode, forming a dielectric layer on the planar layer, forming an emitting material on the planar layer, and forming a cathode on the planar layer.

19. The method of claim 17, wherein the method further comprises forming a common electrode layer on the planar layer, and forming a pixel electrode layer on the planar layer which is electrically coupled to the second drain electrode.