SEMICONDUCTOR STRUCTURE WITH MULTI SPACER AND METHOD FOR FORMING THE SAME

• US 20170084714A1
• Filed: 09/18/2015
• Published: 03/23/2017
• Est. Priority Date: 09/18/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Tsai, Ching-Wei, Wang, Chih-Hao, Leung, Ying-Keung
• Granted Patent: US 9,911,824 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes a bottom spacer formed on a lower part of a sidewall of the gate structure and an upper spacer formed on an upper part of the sidewall of the gate structure. In addition, the upper spacer includes an air gap formed in a dielectric material.

Claims

1. A semiconductor structure, comprising:

a fin structure formed over a substrate;

a gate structure formed across the fin structure;

a bottom spacer formed on a lower part of a sidewall of the gate structure; and

an upper spacer formed on an upper part of the sidewall of the gate structure,

wherein the upper spacer comprises an air gap formed in a dielectric material.

2. The semiconductor structure as claimed in claim 1, further comprising:

a second air gap located adjacent to the upper spacer.

3. The semiconductor structure as claimed in claim 1, wherein

a bottom interlayer dielectric layer formed around the bottom spacer;

an upper interlayer dielectric layer formed around the upper spacer; and

a dummy spacer layer located between the bottom interlayer dielectric layer and the upper interlayer dielectric layer.

4. The semiconductor structure as claimed in claim 3, further comprising:

a second air gap located between the dummy spacer layer and the upper spacer.

5. The semiconductor structure as claimed in claim 3, wherein a top surface of the bottom interlayer dielectric layer is at a position that is lower than a top surface of the bottom spacer.

6. The semiconductor structure as claimed in claim 1, further comprising:

a second air gap located at an end of the upper spacer.

7. The semiconductor structure as claimed in claim 3, wherein the dummy spacer layer and the bottom spacer are made of different materials.

8. The semiconductor structure as claimed in claim 3, wherein the dummy spacer layer is made of aluminum oxide (Al₂O₃), aluminum oxynitride (AlON), or SiN.

26. The semiconductor structure as claimed in claim 1, wherein the dummy spacer layer is made of aluminum oxide (Al₂O₃), or aluminum oxynitride (AlON).

9. A semiconductor structure, comprising:

a fin structure formed over a substrate;

a gate structure formed across the fin structure;

a bottom spacer formed on a lower part of a sidewall of the gate structure;

a source/drain structure formed in the fin structure;

a contact formed over the source/drain structure; and

an upper spacer formed between the contact and an upper part of the sidewall of the gate structure,

wherein the upper spacer comprises an air gap formed in a dielectric material.

10. The semiconductor structure as claimed in claim 9, further comprising:

a bottom interlayer dielectric layer formed around the source/drain structure;

a dummy spacer layer formed over the bottom interlayer dielectric layer; and

an upper interlayer dielectric layer formed over the dummy spacer layer.

11. The semiconductor structure as claimed in claim 10, wherein a top surface of the bottom interlayer dielectric layer is at a position that is lower than a top surface of the bottom spacer.

12. The semiconductor structure as claimed in claim 10, further comprising:

a second air gap located at an end of the dummy spacer layer.

13. The semiconductor structure as claimed in claim 10, wherein the dummy spacer layer and the bottom spacer are made of different materials.

14-20. -20. (canceled)

21. A semiconductor structure, comprising:

a gate structure over a substrate;

a bottom spacer formed at a lower part of a sidewall of the gate structure; and

an upper spacer formed over the bottom spacer,

wherein the upper spacer comprises a first air gap formed in a dielectric material, and the upper spacer is thicker than the bottom spacer.

22. The semiconductor structure as claimed in claim 21, further comprising:

a second air gap exposing a bottom sidewall of the upper spacer.

23. The semiconductor structure as claimed in claim 21, further comprising:

a bottom interlayer dielectric layer formed around the bottom spacer;

a dummy spacer layer formed over the bottom interlayer dielectric layer; and

an upper interlayer dielectric layer formed over the dummy spacer layer.

24. The semiconductor structure as claimed in claim 23, further comprising:

a second air gap separating the dummy spacer layer and the upper spacer.

25. The semiconductor structure as claimed in claim 23, wherein the dummy spacer layer and the bottom spacer are made of different materials.

27. The semiconductor structure as claimed in claim 21, wherein the bottom spacer has a height in a range from about 20 nm to about 60 nm.