FIN STRUCTURES AND MULTI-VT SCHEME BASED ON TAPERED FIN AND METHOD TO FORM
First Claim
1. A method comprising:
- forming a silicon (Si) fin;
forming a hard mask on a top surface of the Si fin;
forming an oxide layer on opposite sides of the Si fin;
implanting a dopant into the Si fin;
recessing the oxide layer to reveal an active Si fin; and
modifying sidewalls of the active Si fin by etching.
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Accused Products
Abstract
A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.
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Citations
13 Claims
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1. A method comprising:
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forming a silicon (Si) fin; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal an active Si fin; and modifying sidewalls of the active Si fin by etching. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A device comprising:
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a silicon (Si) fin, the Si fin having a low-doped active top portion with vertical sidewalls and a highly-doped active bottom portion with tapered sidewalls; and a shallow trench isolation (STI) layer formed on opposite sides of the Si fin. - View Dependent Claims (11, 12, 13)
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Specification