METHOD OF FORMING SPACERS FOR A GATE OF A TRANSISTOR

• US 20170084720A1
• Filed: 09/16/2016
• Published: 03/23/2017
• Est. Priority Date: 09/18/2015
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Inventors: POLLET, Olivier, Posseme, Nicolas
• Granted Patent: US 10,043,890 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0206 during, before or after processing of insulating layers
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

A method is provided for forming spacers of a gate of a field effect transistor, the gate including flanks and a top and being located above a layer of a semiconductor material, the method including a step of forming a dielectric layer covering the gate; after the step of forming, at least one step of modifying the dielectric layer by putting the dielectric layer into presence of a plasma creating a bombarding of light ions; and at least one step of removing the modified dielectric layer including a dry etching performed by putting the modified dielectric layer into presence of a gaseous mixture including at least one first component with a hydrofluoric acid base that transforms the modified dielectric layer into non-volatile residue, and removing the non-volatile residue via a wet clean performed after the dry etching or a thermal annealing of sublimation performed after or during the dry etching.

Claims

1-28. -28. (canceled)

29. A method for forming spacers of a gate of a field effect transistor, with the gate comprising flanks and a top and being located above a layer made of a semiconductor material, the method comprising:

a step of forming a dielectric layer covering the gate of the transistor;

after the step of forming the dielectric layer, at least one step modifying the dielectric layer by putting the dielectric layer into presence of a plasma creating a bombarding of light anisotropic ions according to a favored direction parallel to flanks of the gate, conditions of the plasma, in particular an energy of the light ions and a dose implanted being chosen in such a way as to modify, by implantation of the light ions, at least portions of the dielectric layer that are located on a top of the gate and on either side of the gate and that are perpendicular to the flanks of the gate by retaining portions of the dielectric layer covering the flanks of the gate unmodified or unmodified over an entire thickness thereof;

with the light ions being ions with a hydrogen base and/or a helium base; and

at least one step of removing the modified dielectric layer using selective etching of the modified dielectric layer with respect to the layer made of the semiconductor material and with respect to the unmodified dielectric layer,

wherein the step of removing the modified dielectric layer comprises;

a dry etching performed by putting the modified dielectric layer into presence of a gaseous mixture comprising at least one first component with a hydrofluoric acid base, with hydrofluoric acid transforming the modified dielectric layer into non-volatile residue at an ambient temperature, and

removing, only after the dry etching, of the non-volatile residue at the ambient temperature by a wet clean or by a thermal annealing of sublimation.

30. The method according to claim 29,

wherein the gaseous mixture comprises a second component, and

wherein parameters of the step of removal of the modified dielectric layer, in particular a gas ratio between the first component and the second component used during the dry etching, are provided in such a way that the modified dielectric layer can be selectively etched with respect to the layer made of a semiconductor material and with respect to the unmodified dielectric layer.

31. The method according to claim 30, wherein the first component is generated by evaporation using a liquid source or using a pressurized bottle.

32. The method according to claim 29, wherein said putting into presence is carried out in a chemical reactor.

33. The method according to claim 32,

wherein the reactor comprises an enclosure, and

wherein the putting into presence is carried out at ambient temperature and atmospheric pressure or is carried out at a temperature greater than the ambient temperature and at a pressure less than atmospheric pressure.

34. The method according to claim 29, wherein the dry etching is carried out by the putting into presence of a gaseous mixture comprising hydrofluoric acid (HF).

35. The method according to claim 29, wherein the dry etching is carried out by the putting into presence of a gaseous mixture free from proton acceptor groups.

36. The method according to claim 29, wherein the gaseous mixture comprises a second component with an inert gas base, chosen from nitrogen (N₂) and/or argon (Ar).

37. The method according to claim 36, wherein the gas ratio between the first component and the second component is between 1:

25 and 1;

1.

38. The method according to claim 29, wherein the dry etching is carried out under a temperature between 15°

C. and 80°

C., a pressure between 40 Torr to 760 Torr, and during a duration ranging from a few seconds to a few minutes.

39. The method according to claim 29, wherein the removal of non-volatile residue at ambient temperature comprises a thermal annealing of sublimation carried out at a temperature between 200°

C. and 400°

C.

40. The method according to claim 39, wherein the annealing is carried out under a low pressure between 10.10⁻

3 Torr and 2 Torr.

41. The method according to claim 39, wherein the removal is carried out during a time between 60 seconds and 600 seconds.

42. The method according to claim 29, wherein the removal of non-volatile residue at ambient temperature comprises a wet clean with a deionized water base.

43. The method according to claim 29, comprising, prior to the step of removal of the modified dielectric layer, a vacuum thermal annealing, at a temperature greater than 100°

C.

44. The method according to claim 29, wherein the dielectric layer is formed from one or several dielectric materials of which a dielectric constant k is less than or equal to 7.

45. The method according to claim 29, wherein the dielectric layer is a layer of nitride.

46. The method according to claim 29, wherein the dielectric layer is a layer with a silicon (Si) base.

47. The method according to claim 29, wherein a material of the dielectric layer is taken from:

SiCO, SiC, SiCN, SiON, SiOCN, SiCBN, SiOCH, and SiO_x, where x is a positive integer.

48. The method according to claim 29,

wherein the semiconductor material is silicon, and

wherein the step of removal of the modified dielectric layer is carried out partially at least by dry etching selectively with silicon (Si) and/or with a layer of silicon oxide (SiO₂).

49. The method according to claim 29, further comprising forming a hard mask of at least one silicon oxide (SiO₂) layer, located on the gate or a shallow trench isolation.

50. The method according to claim 29, further comprising a single step of modification carried out in such a way as to modify the dielectric layer in all of its thickness over all of the surfaces parallel to a plane of a substrate whereon the gate rests and to not modify the dielectric layer in all of its thickness over all of the surfaces perpendicular to the plane.

51. The method according to claim 29,

wherein the layer made of a semiconductor material is taken from:

silicon (Si), germanium (Ge), silicon-germanium (SiGe), and

wherein the light ions are taken from helium and/or hydrogen and/or ammonia.

52. The method according to claim 29, wherein the light ions are with a hydrogen base and the flow rate of the light ions with the hydrogen base is between 10 sccm and 500 sccm, with the light ions being taken from:

H, H+, H₂+, and H₃+.

53. The method according to claim 29, wherein the light ions are with a helium base and the flow rate of the light ions with a helium base is between 50 sccm and 500 sccm.

54. The method according to claim 29, wherein the step of modification of the dielectric layer is carried out with a power of polarization or power of source between 20V and 500V, with a pressure between 5 mTorr and 100 mTorr, at a temperature between 10°

C. and 100°

C., during a duration from a few seconds to a few hundred seconds.

55. The method according to claim 29, wherein the step of modification of the dielectric layer carried out using a plasma modifies the dielectric layer in a continuous manner from the surface of the dielectric layer and over a thickness between 1 nm and 30 nm.

56. The method according to claim 29, wherein the transistor is a transistor of a FDSOI type or of a FinFET type.