SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

• US 20170084727A1
• Filed: 11/30/2016
• Published: 03/23/2017
• Est. Priority Date: 12/19/2014
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Naito, Tatsuya
• Granted Patent: US 10,109,726 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/82285 Complementary vertical transistors
• CPC Class Codes: H01L 27/0825 Combination of vertical direct transistors of the same conductivity type having different characteristics,(e.g. Darlington transistors)
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A semiconductor device including a mesa portion formed on a front surface side of a semiconductor substrate; a floating portion formed on the front surface side of the semiconductor substrate; a trench formed surrounding the floating portion and separating the mesa portion from the floating portion; an electrode formed inside the trench; and an outside wiring portion formed along an arrangement direction of the mesa portion and the floating portion, outside the region surrounded by the trench. An edge of the outside wiring portion on the mesa portion and floating portion side includes a protruding portion formed in at least part of a region opposite the floating portion and protruding beyond the trench toward the floating portion side, and a recessed portion formed in at least part of a region opposite the mesa portion and recessed to the outside wiring portion side farther than the protruding portion.

Claims

1. A semiconductor device comprising:

a mesa portion formed on a front surface side of a semiconductor substrate;

a floating portion formed on the front surface side of the semiconductor substrate;

a trench that is formed surrounding the floating portion and separates the mesa portion from the floating portion;

an electrode formed inside the trench; and

an outside wiring portion formed along an arrangement direction of the mesa portion and the floating portion, outside of a region surrounded by the trench, wherein

an edge of the outside wiring portion on the mesa portion and floating portion side includes;

a protruding portion that is formed in at least a portion of a region opposite the floating portion and protrudes beyond the trench toward the floating portion side; and

a recessed portion that is formed in at least a portion of a region opposite the mesa portion and is recessed to the outside wiring portion side farther than the protruding portion.

2. The semiconductor device according to claim 1, wherein

the semiconductor substrate has a first conductivity type, and

the semiconductor device further comprises a well region that has a second conductivity type and is formed between an end of the semiconductor substrate and the mesa portion and floating portion.

3. The semiconductor device according to claim 2, wherein

the mesa portion has a base region with a second conductivity type, and

the base region and the well region are connected to each other.

4. The semiconductor device according to claim 3, wherein

the recessed portion is recessed to the outside wiring portion side to a position enabling the base region and the well region to connect to each other.

5. The semiconductor device according to claim 3, wherein

a tip of the recessed portion is arranged farther to the outside wiring portion side than a position that protrudes by 0.75 times a depth of the base region toward the inside of the mesa portion from an end of the well region.

6. The semiconductor device according to claim 2, wherein

a tip of the recessed portion is arranged farther on the outside wiring portion side than the trench.

7. The semiconductor device according to claim 2, wherein

the floating portion has a second conductivity type, and

a region having the second conductivity type in the floating portion that is covered by the protruding portion is connected to the trench.

8. The semiconductor device according to claim 7, wherein

the protruding portion has a length that enables the region of the floating portion having the second conductivity type to connect to the trench below the protruding portion.

9. The semiconductor device according to claim 8, wherein

length of a region of the protruding portion overlapping with the floating portion is less than or equal to 0.75 times a depth of the floating portion.

10. The semiconductor device according to claim 1, wherein

width of the protruding portion is less than width of the floating portion.

11. The semiconductor device according to claim 1, wherein

width of the recessed portion is greater than width of the mesa portion.

12. A semiconductor device manufacturing method comprising:

on a front surface side of a semiconductor substrate, forming a trench that surrounds a predetermined region, a floating portion surrounded by the trench, and a mesa portion separated from the floating portion;

forming an electrode in the trench and forming an outside wiring portion along an arrangement direction of the mesa portion and the floating portion outside of the region surrounded by the trench; and

doping the mesa portion and the floating portion with impurities having a predetermined conductivity type, using the outside wiring portion as a mask, and diffusing the impurities, wherein

forming the outside wiring portion includes forming, on an edge of the outside wiring portion that is on the mesa portion and floating portion side;

a protruding portion that is arranged in at least a portion of a region opposite the floating portion and protrudes beyond the trench toward the floating portion side; and

a recessed portion that is arranged in at least a portion of a region opposite the mesa portion and is recessed to the outside wiring portion side farther than the protruding portion.

13. The semiconductor device manufacturing method according to claim 12, wherein

the semiconductor substrate has a first conductivity type, and

the semiconductor device manufacturing method further comprises, before the forming the trench, forming a well region that has a second conductivity type between an end of the semiconductor substrate and the mesa portion and floating portion.

14. The semiconductor device manufacturing method according to claim 13, wherein

the doping with the impurities and diffusing the impurities includes doping with impurities having a second conductivity type and diffusing the impurities to form a base region connected to the well region in the mesa portion.

15. The semiconductor device manufacturing method according to claim 13, wherein

the doping with the impurities and diffusing the impurities includes doping with impurities having a second conductivity type, diffusing the impurities, and connecting a region having the second conductivity type in the floating portion covered by the protruding portion to the trench.