CONFIGURABLE CACHE ARCHITECTURE

• US 20170091112A1
• Filed: 11/24/2015
• Published: 03/30/2017
• Est. Priority Date: 09/30/2015
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Emma, Philip G.
• Application Number:
  US14/949,946
• Publication Number:
  US 20170091112A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0877 Cache access modes
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/221 Static RAM
• CPC Class Codes: G06F 2212/225 Hybrid cache memory, e.g. having both volatile and non-volatile portions
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode

Abstract

Embodiments relate to providing a configurable cache memory. An aspect includes configuring, via a cache configuration logic, a plurality of cache memories that make up the configurable cache memory into a selected mode, wherein the plurality of cache memories comprise physically separate memory modules, and wherein the plurality of cache memories are linked by the cache configuration logic. Another aspect includes operating the configurable cache memory in the selected mode, wherein the configurable cache memory is capable of operating in a plurality of modes.

Claims

1. A computer implemented method for providing a configurable cache memory, the method comprising:

configuring, via a cache configuration logic, a plurality of cache memories that make up the configurable cache memory into a selected mode, wherein the plurality of cache memories comprise physically separate memory modules, and wherein the plurality of cache memories are linked by the cache configuration logic; and

operating the configurable cache memory in the selected mode, wherein the configurable cache memory is capable of operating in a plurality of modes, the plurality of modes comprises operating the plurality of cache memories of the configurable cache memory as separate cache memories, wherein each of the plurality of cache memories is assigned to a respective single thread during operation of the configurable cache memory, wherein the plurality of cache memories are kept coherent with one another via a coherency notification interface that notifies each of the plurality of cache memories regarding the fetches and stores that were performed in the other plurality of cache memories.

3. The method of claim 1, wherein the selected mode comprises operating the plurality of cache memories as a single cache.

4. The method of claim 3, wherein the selected mode comprises operating the single cache in an extended mode.

5. The method of claim 3, wherein the selected mode comprises operating the single cache in a double line size mode.

6. The method of claim 1, wherein the selected mode comprises operating the plurality of cache memories in a hierarchical mode.

7. The method of claim 6, wherein a first cache memory of the plurality of cache memories comprises a primary cache comprising static random access memory (SRAM), and a second cache memory of the plurality of cache memories comprises a victim cache comprising dynamic random access memory (DRAM).

2. (canceled)