INTERNAL SERIAL INTERFACE

• US 20170091143A1
• Filed: 09/29/2016
• Published: 03/30/2017
• Est. Priority Date: 09/30/2015
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Ross, James Henry, Banowetz, Matthew Lee
• Granted Patent: US 10,248,612 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4286 using a handshaking protocol, e.g. RS232C link
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A simplified serial interface for a communications device. The serial interface includes an RF front end and a transmit block and at least one receive block located on different dies. The receive block is activated by a clock generator that is separate than the system clock. The at least one receive block can inhibit transmission of an enable signal to the receive block and inhibit operation of an oscillator of the interface.

Claims

1. A communications interface device comprising:

a radio frequency front end (RFFE) configured to receive input data signals and a first clock signal;

a serial interface configured to receive data signals from the RFFE and includes a transmit block that provides data and enable signals to at least one receive block, the receive block being associated with a component other than the RFFE; and

a clock generator configured to be enabled by the RFFE to provide a second clock signal when data is to be transmitted via the interface so that the serial interface transmit block receives the second clock signal.

2. The device of claim 1 wherein the at least one receive block includes a plurality of receive blocks configured to receive data signals, enable signals and clock signals from the at least one transmit block.

3. The device of claim 2 wherein the plurality of receive blocks receive a common enable signal.

4. The device of claim 2 wherein the plurality of receive blocks are individually enabled by the transmit block.

5. The device of claim 1 wherein the clock generator is activated by the RFFE when data is received by the RFFE indicates that the data being provided to the at least one receive block has changed.

6. The device of claim 1 wherein the clock generator provides a clock signal and a transmit signal to the transmit block of the interface when enabled by the RFFE.

7. The device of claim 6 wherein the clock generator and the transmit block are disabled when the data has been transmitted.

8. The device of claim 1 further comprising a downstream device configured to receive the data from the at least one receive block.

9. The device of claim 8 wherein the downstream device includes an antenna switch module or a band switch.

10. The device of claim 8 wherein the RFFE and the transmit block are formed on a first die, and the at least one receive block and downstream device are formed on a second die.

11. The device of claim 8 wherein the downstream device includes a detector configured to determine when the receive block and downstream device is capable of receiving the data from the receive block and the downstream device communicates with the receive block to inhibit enablement of the receive block until the receive unit and downstream device is capable of receiving data.

12. The device of claim 11 wherein the downstream device includes a power on reset (POR) detector, and the enable line of the receive block has a switch enabled pull down resistor configured to inhibit transmission of the enable signal.

13. A communications device comprising:

a radio frequency front end (RFFE) configured to receive input data signals and a first clock signal;

a serial interface configured to receive data signals from the RFFE and includes a transmit block configured to provide data and enable signals to at least one receive block, the at least one receive block being associated with a component other than the RFFE; and

a downstream device configured to receive the data from the at least one receive block, the downstream device including a detector configured to determine when the at least one receive block and downstream device are capable of receiving the data from the at least one receive block, the downstream device configured to communicate with the at least one receive block to inhibit enablement of the receive block until the receive block and downstream device are capable of receiving data.

14. The device of claim 13 further comprising a clock generator configured to be enabled by the RFFE to provide a second clock signal to the serial interface transmit block when data is to be transmitted via the interface.

15. The device of claim 14 wherein the clock generator provides a clock signal and a transmit signal to the transmit block of the interface when enabled by the RFFE.

16. The device of claim 15 wherein the clock generator and the transmit block are disabled when the data has been transmitted.

17. The device of claim 13 wherein the at least one receive block includes a plurality of receive blocks configured to receive data signals, enable signals and clock signals from the at least one transmit block.

18. The device of claim 17 wherein the plurality of receive blocks receive a common enable signal.

19. The device of claim 17 wherein the plurality of receive blocks are individually enabled by the transmit block.

20. The device of claim 13 wherein the downstream device includes an antenna switch module or a band switch.

21. The device of claim 13 wherein the RFFE and the transmit block are formed on a first die, and the at least one receive block and downstream device are formed on a second die.

22. The device of claim 13 wherein the downstream device includes a power on reset (POR) detector, and the enable line of the receive block has a switch enabled pull down resistor configured to inhibit transmission of the enable signal.