×

MEMORY CONTROLLER WITH DYNAMIC CORE-TRANSFER LATENCY

  • US 20170092343A1
  • Filed: 03/24/2015
  • Published: 03/30/2017
  • Est. Priority Date: 03/26/2014
  • Status: Active Grant
First Claim
Patent Images

1. A method of operation within a memory controller having a controller core and a physical signaling interface, the method comprising:

  • outputting a request for read data from the controller core to the physical signaling interface, the request for read data specifying one of at least two memory components from which the read data is to be retrieved;

    outputting a memory read request from the physical signaling interface to the one of at least two memory components in accordance with the request for read data;

    receiving the read data via the physical signaling interface following output of the memory read request; and

    transferring the read data from the physical signaling interface to the controller core at either a first time or a second time according to whether the one of at least two memory components specified in the request for read data is a first memory component of the at least two memory components or a second memory component of the at least two memory components.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×