MEMORY CONTROLLER WITH DYNAMIC CORE-TRANSFER LATENCY

• US 20170092343A1
• Filed: 03/24/2015
• Published: 03/30/2017
• Est. Priority Date: 03/26/2014
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Palmer, Robert E., Stonecypher, William F.
• Granted Patent: US 9,892,771 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

In a memory controller having a controller core and a physical signaling interface, the controller core outputs a request for read data to the physical signaling interface specifying one of at least two memory components from which the read data is to be retrieved. In response to the request for read data, the physical signaling interface outputs a memory read request to the specified memory component, receives the read data from the specified memory component, and transfers the read data to the controller core at either a first time or a second time according to whether the specified memory component is a first memory component or second memory component of the at least two memory components.

Claims

1. A method of operation within a memory controller having a controller core and a physical signaling interface, the method comprising:

outputting a request for read data from the controller core to the physical signaling interface, the request for read data specifying one of at least two memory components from which the read data is to be retrieved;

outputting a memory read request from the physical signaling interface to the one of at least two memory components in accordance with the request for read data;

receiving the read data via the physical signaling interface following output of the memory read request; and

transferring the read data from the physical signaling interface to the controller core at either a first time or a second time according to whether the one of at least two memory components specified in the request for read data is a first memory component of the at least two memory components or a second memory component of the at least two memory components.

2. The method of claim 1 wherein receiving the read data via the signaling interface comprises receiving the read data in response to transitions of a strobe signal output by the one of at least two memory components, and wherein transferring the read data from the physical signaling interface to the controller core comprises transferring the read data to the controller core at times indicated by transitions of a clock signal, the clock signal defining a clock domain within the controller core that is mesochronous with respect to a timing domain defined by transitions of the strobe signal.

3. The method of claim 1 wherein each memory component of the least two memory components is a component of a respective rank of two or more memory components.

4. The method of claim 1 wherein transferring the read data from the physical signaling interface to the controller core at either a first time or a second time comprises determining a first estimated time of arrival within the physical signaling interface for read data received from the first memory component and a second estimated time of arrival within the physical signaling interface for read data received from the second memory component.

5. The method of claim 4 wherein transferring the read data from the physical signaling interface to the controller core at either the first time or the second time further comprises transferring the read data from the physical signaling interface to the controller at a time, based at least in part, on either the first estimated time or the second estimated time according to whether the one of at least two memory components specified in the request for read data is the first memory component or the second memory component.

6. The method of claim 4 further comprising determining a time of arrival of the read data within the physical signaling interface and updating either the first estimated time or the second estimated time according to whether the one of at least two memory components specified in the request for read data is the first memory component or the second memory component.

7. The method of claim 6 wherein determining the time of arrival of the read data within the physical signaling interface comprises determining an elapsed time between the time of arrival of the read data within the physical signaling interface and receipt within the physical signaling interface of one or more signals from the controller core corresponding to the request for read data.

8. The method of claim 4 wherein determining the first estimated time of arrival within the signaling interface for read data received from the first memory component comprises adjusting the first estimated time of arrival in response to timing determinations made for each of a sequence of memory read transactions executed with respect to the first memory component.

9. The method of claim 8 wherein at least one memory read transaction of the sequence of memory read transactions is a dummy read transaction.

10. The method of claim 4 wherein determining the first estimated time of arrival comprises issuing one or more dummy read requests to the first memory component and determining respective times of arrival, within the physical signaling interface, of read data corresponding to the one or more dummy read requests.

11. A memory controller component comprising:

a controller core to output a request for read data, the request for read data specifying one of at least two memory components from which the read data is to be retrieved;

a physical signaling interface to;

receive the request for read data from the controller core,

output a memory read request to the specified one of at least two memory components,

receive the read data following output of the memory read request, and

transfer the read data to the controller core at either a first time or a second time according to whether the specified one of at least two memory components is a first memory component of the at least two memory components or a second memory component of the at least two memory components.

12. The memory controller component of claim 11 wherein the physical signaling interface to receive the read data and transfer the read data to the controller core comprises circuitry to receive the read data in response to transitions of a strobe signal output by the specified one of at least two memory components and to transfer the read data to the controller core at times indicated by transitions of a clock signal, the clock signal defining a clock domain within the controller core that is mesochronous with respect to a timing domain defined by transitions of the strobe signal.

13. The memory controller component of claim 11 wherein each memory component of the least two memory components is a component of a respective rank of two or more memory components.

14. The memory controller component of claim 11 wherein the physical signaling interface to transfer the read data to the controller core at either a first time or a second time comprises circuitry to determine a first estimated time of arrival within the physical signaling interface for read data received from the first memory component and a second estimated time of arrival within the physical signaling interface for read data received from the second memory component.

15. The memory controller component of claim 14 wherein the physical signaling interface to transfer the read data to the controller core at either the first time or the second time further comprises circuitry to transfer the read data to the controller at a time, based at least in part, on either the first estimated time or the second estimated time according to whether the specified one of at least two memory components is the first memory component or the second memory component.

16. The memory controller component of claim 14 wherein the circuitry to determine the first estimated time of arrival comprises circuitry to (i) determine a time of arrival of the read data within the physical signaling interface and (ii) update either the first estimated time or the second estimated time according to whether the specified one of at least two memory components is the first memory component or the second memory component.

17. The memory controller component of claim 16 wherein the circuitry to determine the time of arrival of the read data within the physical signaling interface comprises circuitry to determine an elapsed time between the time of arrival of the read data within the physical signaling interface and receipt of one or more signals from the controller core corresponding to the request for read data.

18. The memory controller component of claim 14 wherein the circuitry to determine the first estimated time of arrival comprises circuitry to adjust the first estimated time of arrival in response to timing determinations made for each of a sequence of memory read transactions executed with respect to the first memory component.

19. The memory controller component of claim 14 wherein the physical signaling face is further to issue one or more dummy read requests to the first memory component and the circuitry to determine the first estimated time of arrival comprises circuitry determine respective times of arrival of read data corresponding to the one or more dummy read requests.

20. A memory controller component having a controller core and a physical signaling interface, the memory controller comprising:

means for outputting a request for read data from the controller core to the physical signaling interface, the request for read data specifying one of at least two memory components from which the read data is to be retrieved;

means for outputting a memory read request from the physical signaling interface to the one of at least two memory components in accordance with the request for read data;

means for receiving the read data via the physical signaling interface following output of the memory read request; and

means for transferring the read data from the physical signaling interface to the controller core at either a first time or a second time according to whether the one of at least two memory components specified in the request for read data is a first memory component of the at least two memory components or a second memory component of the at least two memory components.