MULTI-GATE NOR FLASH THIN-FILM TRANSISTOR STRINGS ARRANGED IN STACKED HORIZONTAL ACTIVE STRIPS WITH VERTICAL CONTROL GATES
First Claim
1. A memory structure, comprising:
- a semiconductor substrate having a substantially planar surface;
a first stack of active strips and a second stack of active strips formed over the surface of the semiconductor substrate and separated by a predetermined distance, wherein each stack of active strips comprises two or more active strips provided one on top of another on two or more isolated planes and being substantially aligned lengthwise with each other along a first direction substantially parallel to the planar surface, and wherein each active strip comprises a first semiconductor layer of a first conductivity type provided between second and third semiconductor layers each of a second conductivity type;
a charge-trapping material; and
a plurality of conductors each provided between the first stack of active strip and the second stack of active strips, wherein each conductor is separated from each stack of active strips by the charge-trapping material and extends lengthwise in a second direction that is substantially perpendicular to the planar surface.
1 Assignment
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Accused Products
Abstract
Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.
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Citations
58 Claims
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1. A memory structure, comprising:
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a semiconductor substrate having a substantially planar surface; a first stack of active strips and a second stack of active strips formed over the surface of the semiconductor substrate and separated by a predetermined distance, wherein each stack of active strips comprises two or more active strips provided one on top of another on two or more isolated planes and being substantially aligned lengthwise with each other along a first direction substantially parallel to the planar surface, and wherein each active strip comprises a first semiconductor layer of a first conductivity type provided between second and third semiconductor layers each of a second conductivity type; a charge-trapping material; and a plurality of conductors each provided between the first stack of active strip and the second stack of active strips, wherein each conductor is separated from each stack of active strips by the charge-trapping material and extends lengthwise in a second direction that is substantially perpendicular to the planar surface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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40. A semiconductor manufacturing process, comprising:
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providing a semiconductor substrate and forming circuitry therein and thereon; providing a plurality of active layers and buried contacts over the semiconductor substrate, each active layer comprising a first semiconductor layer of a first conductivity between second and third semiconductor layers of a second conductivity, wherein each active layer is electrically isolated from a lower active layer or the semiconductor substrate by a dielectric layer, except at the buried contacts, wherein the buried contacts connect one or more of the second or third semiconductor layers of each active layer to the circuitry of the semiconductor substrate; patterning and etching the plurality of active layers anisotropically to provide a first set of trenches with sidewalls running lengthwise in a first direction that is substantially parallel to a surface of the semiconductor substrate along a first direction; providing a charge-trapping material conformally over the sidewalls of the trenches; filling the trenches with a conductive material; and patterning and etching a portion of the conductive material, such that the remaining conductive material forms a plurality of conductors that extends lengthwise along a second direction that is substantially perpendicular to the surface of the semiconductor substrate; and providing a layer of dielectric material over the active layers except at the conductors and a plurality of contacts that is exposed and which is connected to the circuitry in the semiconductor substrate; and providing conductive wiring that connects the conductors and the exposed contacts. - View Dependent Claims (41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52)
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- 53. A NOR string array formed over a planar surface of a semiconductor substrate, comprising a first NOR string and a second NOR string, each NOR string comprising thin-film storage transistors formed along an active strip extending lengthwise along a first direction parallel to the planar surface, wherein the thin film storage transistors in each NOR string share a common drain terminal and a common source terminal, and wherein each storage transistor of the first NOR string is electrically connected to a corresponding storage transistor of the second NOR string by a conductor that extends lengthwise along a second direction which is perpendicular to the planar surface.
Specification