CAPACITIVE-COUPLED NON-VOLATILE THIN-FILM TRANSISTOR STRINGS IN THREE DIMENSIONAL ARRAYS

• US 20170092371A1
• Filed: 08/26/2016
• Published: 03/30/2017
• Est. Priority Date: 09/30/2015
• Status: Active Grant

• Current Assignee: Sunrise Memory Corporation
• Original Assignee: Sunrise Memory Corporation
• Inventors: Harari, Eli
• Granted Patent: US 10,121,553 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/92 Capacitors having potential barriers
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Multi-gate NOR flash thin-film transistor (TFT) string arrays are organized as three dimensional stacks of active strips. Each active strip includes a shared source sublayer and a shared drain sublayer that is connected to substrate circuits. Data storage in the active strip is provided by charge-storage elements between the active strip and a multiplicity of control gates provided by adjacent local word-lines. The parasitic capacitance of each active strip is used to eliminate hard-wire ground connection to the shared source making it a semi-floating, or virtual source. Pre-charge voltages temporarily supplied from the substrate through a single port per active strip provide the appropriate voltages on the source and drain required during read, program, program-inhibit and erase operations. TFTs on multiple active strips can be pre-charged separately and then read, programmed or erased together in a massively parallel operation.

Claims

1. A memory circuit, comprising:

a semiconductor substrate having a substantially planar surface and including circuitry formed at the surface; and

a memory array formed above the semiconductor substrate comprising a plurality of thin-film storage transistors arrayed along substantially mutually perpendicular first, second and third directions, the memory array being formed out of a semiconductor structure comprising a plurality of active strips (i) separated from each other along the first direction by a space of a predetermined distance, (ii) isolated from each other, along the second direction by a first dielectric material, and (iii) extending lengthwise along the third direction, wherein (a) each active strip comprises a first semiconductor sublayer of a first conductivity type provided between second and third semiconductor sublayers that are each of a second conductivity type, the first, second and third semiconductor sublayers providing, respectively, channel, source and drain regions of the thin-film storage transistors, (b) the thin-film storage transistors of each active strip sharing common source regions, and (c) the shared source region is electrically floating relative to the circuitry formed in the semiconductor substrate, except when one or more of the channel regions of the active strip is rendered conducting.

2. The memory circuit of claim 1, wherein the second direction is substantially perpendicular to a surface of the semiconductor substrate.

3. The memory circuit of claim 1, wherein the second direction is substantially parallel to a surface of the semiconductor substrate.

4. The memory circuit of claim 1, further comprising, within the space separating the active strips along the first direction:

a charge-trapping material; and

a first plurality of conductors provided along the third direction, each conductor extending lengthwise along the second direction, such that each conductor is provided adjacent one or more active strips, separated from each adjacent active strips by the charge-trapping material.

5. The memory circuit of claim 4, wherein the first plurality of conductors each provide a gate electrode to one or more thin-film storage transistors on active strips adjacent the conductor.

6. The memory circuit of claim 5, wherein each of the first plurality of conductors is adjacent to more than one active strip along the first direction.

7. The memory circuit of claim 5, further comprising a second plurality of conductors formed between the planar surface and the active strips along the first direction, the second plurality of conductors each connecting a portion of the circuitry at the surface of the semiconductor substrate to selected ones of the first plurality of conductors that serve as gate electrodes of the thin-film storage transistors.

8. The memory circuit of claim 7, further comprising a third plurality of conductors formed above the active strips along the first direction, the third plurality of conductors each connecting a portion of the circuitry at the surface of the semiconductor substrate to selected ones of the first plurality of conductors that serve as gate electrodes of the thin-film storage transistors.

9. The memory circuit of claim 8, wherein the selected ones of the first plurality of conductors connected to the second plurality of conductors and the selected ones of the first plurality of conductors connected to the third plurality of conductors are provided on opposite sides of an active strip.

10. The memory circuit of claim 8, wherein each thin-film storage transistor is associated with a numeric address, wherein the thin-film storage transistors associated with even addresses are connected to the second plurality of conductors and wherein the thin-film storage transistors associated with odd addresses are connected to the third plurality of conductors.

11. The memory circuit claim 5, further comprising a second plurality of conductors formed above the active strips along the first direction, the second plurality of conductors each connecting the circuitry at the surface of the semiconductor substrate to selected ones of the first plurality of conductors that serve as gate electrodes of the thin-film storage transistors.

12. The memory circuit of claim 5, wherein a portion of the charge-trapping material adjacent each of the one or more thin film storage transistors constitute a data storage element for that thin-film storage transistor.

13. The memory circuit of claim 12, wherein the data storage element has a data retention time shorter than a year and a program/erase cycle endurance greater than 10,000 program/erase cycles.

14. The memory circuit of claim 1, wherein each thin-film storage transistor has a native enhancement mode threshold voltage.

15. The memory circuit of claim 1, wherein the circuitry at the surface of the semiconductor substrate comprises voltage sources for providing predetermined voltages for transistor operations.

16. memory circuit of claim 15, wherein the predetermined voltage comprise at least one of:

program, program-inhibit, reading and erasing voltages.

17. The memory circuit of claim 15, wherein each thin-film storage transistor has a variable threshold voltage that is set using Fowler-Nordheim tunneling or direct tunneling.

18. The memory circuit of claim 15, wherein the variable threshold voltage is set to a level corresponding to one of two or more charge states.

19. The memory circuit of claim 1, wherein the first semiconductor sublayer is substantially thinner than a width of the active strip measured along the first direction.

20. The memory circuit of claim 1, further comprising a dopant diffusion-blocking layer between the first and second semiconductor sublayers.

21. The memory circuit of claim 20, wherein the dopant diffusion-blocking layer comprises a dielectric material that is less than three nanometers thick.

22. The memory circuit of claim 1, further providing buried contact structures to connect one of the second and third semiconductor sublayer of each active strip to circuitry at the surface of the semiconductor substrate.

23. The memory circuit of claim 22, wherein the buried contact structures allow erase, program, program-inhibit and read voltages to be set independently for each active strip.

24. The memory circuit of claim 1, wherein the first, second and third semiconductor sublayers each comprise polysilicon.

25. The memory circuit of claim 4, wherein the thin-film storage transistors along each active strip are connected in parallel relative to each other and organized into one or more NOR-type memory strings (“

NOR strings”

).

26. The memory circuit of claim 25, wherein each active strip comprises a NOR string along its length on each of two sides of the active strip.

27. The memory circuit of claim 25, further comprising electrically conductive material providing shielding between thin film transistors on adjacent NOR strings.

28. The memory circuit of claim 5, wherein the channel region of each thin-film storage transistor is electrically connected to the semiconductor substrate.

29. The memory circuit of claim 28, wherein the channel region of each thin-film storage transistor is connected to the semiconductor substrate by a pillar of semiconductor material of the first conductivity type.

30. The memory circuit of claim 29, wherein the semiconductor substrate provides the channel region of each thin-film storage transistor a predetermined back bias voltage that suppresses sub-threshold leakage during read operations.

31. The memory circuit of claim 30, wherein the predetermined back bias voltage is negative.

32. The memory circuit of claim 28, wherein the pillar of semiconductor material comprises P⁻

doped polysilicon and the second and third semiconductor sublayers comprise N⁺ doped polysilicon.

33. The memory circuit of claim 28, wherein the source region and the drain regions of each thin-film storage transistor are set to a voltage higher than a threshold voltage for the thin-film storage transistor when in the non-conducting state.

34. The memory circuit of claim 28, wherein the semiconductor substrate applies to the channel region of each thin-film storage transistor one or more erase voltage pulses during block erase operations, while all the first plurality of conductors are held at a ground voltage.

35. The memory circuit of claim 5, wherein the second and third semiconductor sublayers are set to receive one or more erase voltage pulses while the first plurality of conductors are held at ground voltage during a block erase operation.

36. The memory circuit of claim 5, wherein the channel length is sufficiently short to effectuate erase through lateral hopping conduction and tunneling out of stored charge under fringing electric fields between the first, second and third semiconductor sublayers and corresponding ones of the first plurality of conductors.

37. The memory circuit of claim 5, wherein the first plurality of conductors each comprise one of N⁺ doped polysilicon, P⁺ doped Polysilicon, a refractory metal of a high work function with respect to silicon dioxide, or silicides or polycides.

38. The memory circuit of claim 1, wherein each active strip further comprises a conductive sublayer that comprises one or more of:

a metal, a silicide or a polycide, the conductive sublayer being in contact with, and in substantial alignment lengthwise with, one or both of the second or third semiconductor sublayers.

39. The memory circuit of claim 4, wherein the charge-trapping material comprises one or more layers of silicon nitride or a bandgap engineered oxide-nitride-oxide dielectric layer.

40. The memory circuit of claim 39, wherein each layer of silicon nitride is provided between layers of silicon oxide.

41. The memory circuit of claim 5 wherein, for each of the first plurality of conductors, when a voltage exceeding a predetermined value is applied to the conductor relative to the first, second and third semiconductor sublayers, the charge-trapping material adjacent the conductor accumulates an electric charge corresponding to one or more threshold voltages representative of the stored data.

42. The memory circuit of claim 4, wherein each of the first plurality of conductors, the charge-trapping material adjacent that conductor and the first, second and third semiconductor sublayers form a variable-threshold storage element.

43. The memory circuit of claim 42, wherein each storage element stores more than one data bit.

44. The memory circuit of claim 25, wherein the floating one of the second and third semiconductor sublayers provides an intrinsic capacitor for each NOR string between the floating semiconductor sublayer and corresponding ones of the first plurality of conductors adjacent thereto.

45. The memory circuit of claim 44, wherein each thin-film storage transistor of each NOR string is individually addressable for programming, programming-inhibiting, erasing or reading operations.

46. The memory circuit of claim 25, wherein each thin-film storage transistor of each NOR string is randomly accessed.

47. The memory circuit of claim 46, further comprising a second plurality of conductors that are provided along the first direction, wherein the thin-film transistors of the semiconductor structure are organized into addressable memory pages each comprising one thin-film storage transistor from each of a plurality of adjacent NOR strings at the same position (“

plane”

) along the second direction, each addressable memory page being accessible by one of the second plurality of conductors.

48. The memory circuit of claim 46, wherein the thin-film storage transistors are organized into addressable memory slices each comprising a plurality of adjacent memory pages at different positions (“

planes”

) along the second direction.

49. The memory circuit of claim 48, wherein the thin-film storage transistors are organized into addressable memory quadrants, each quadrant comprising a plurality of adjacent memory slices.

50. The memory circuit of claim 49, wherein the thin-film storage transistors are organized into memory blocks, each memory block comprising a two-by-two configuration of adjacent memory quadrants.

51. The memory circuit of claim 50, wherein thin-film storage transistors in a first one of the quadrants and a second one of the quadrants share a common set of circuitry at the surface of the semiconductor substrate.

52. The memory circuit of claim 51, wherein the common set of circuitry at the surface of the substrate includes voltage sources and sense amplifiers.

53. The memory circuit of claim 51, wherein the thin-film storage transistors in one or more slices in the first quadrant provide reference threshold voltages for corresponding thin-film storage transistors in selected slices of the second quadrant during program and read operations.

54. The memory circuit of claim 50, wherein, during an erase operation, selected one or more blocks that are previous tagged for the erase operation are erased concurrently.

55. The memory circuit of claim 54, wherein, following the concurrent erase operation, the blocks that have been determined to have been erased are untagged.

56. The memory circuit of claim 54, wherein thin-film storage transistors on all strings, pages or slices that are not selected for programming or reading operations are program-inhibited or floated.

57. The memory circuit of claim 50 wherein, during an erase operation, selected thin-film storage transistors of one or more memory blocks are erased together in parallel.

58. The memory circuit of claim 50 wherein, within each memory block thin-film storage transistors of one or more memory slices are randomly selected and erased together.

59. The memory circuit of claim 50, wherein thin-film storage transistors in a first group of one or more memory blocks are erased together, while thin-film storage transistors of a second group of one or more memory blocks are programmed or read together.

60. The memory circuit of claim 25, wherein each NOR string is individually addressable, and wherein a thin-film transistor in each of a plurality of the NOR strings are programmed, erased, and read simultaneously.

61. The memory circuit of claim 44, wherein a selected group of thin-film storage transistors in each NOR string charge the intrinsic capacitor.

62. The memory circuit of claim 61, wherein members of the selected group and other thin-film storage transistors in each NOR string share the same transistor characteristics.

63. The memory circuit of claim 61, wherein the charged intrinsic capacitor provides a local voltage source on the NOR string for a thin-film storage transistor that is being programmed, program-inhibited, erased or read.

64. The memory circuit of claim 63, wherein the local voltage source does not vary in voltage by more than a predetermined amount during programming, program-inhibition, erase and read of the thin-film storage transistor.

65. The memory circuit of claim 64 wherein more than 128 of the first plurality of conductors are provided adjacent to each active strip.

66. The memory circuit of claim 63, wherein the thin-film storage transistor is programmed using either direct tunneling or Fowler-Nordheim tunneling, and wherein the electrons trapped in the charge-trapping layer are supplied from the intrinsic capacitor.

67. The memory circuit of claim 61, wherein the circuitry at the surface of the semiconductor substrate charges the intrinsic capacitor selectively to one of:

a read voltage, a program voltage, a program-inhibit voltage, an erase voltage, or voltages for setting the programmable thin film transistors of NOR strings designated as reference strings.

68. The memory circuit of claim 61 wherein, during a read operation of a selected thin-film storage transistor in each of a selected plurality of NOR strings, (i) the selected group of thin-film storage transistors in each of the selected NOR strings charge the intrinsic capacitor of the floating one of the second and third semiconductor sublayers of the NOR string to a predetermined voltage from the circuitry at the surface of the semiconductor substrate;

(ii) thereafter, the other one of the second and third semiconductor sublayers of each selected NOR string is charged to a read-sense voltage and is connected to a sense amplifier in the circuitry at the surface of the semiconductor substrate; and

(iii) corresponding ones of the first plurality of conductors associated with the selected thin-film storage transistors are set to a sequence of predetermined read voltages or a voltage ramp while all unselected conductors of the first plurality of conductors are held in their non-conducting state.

69. The memory circuit of claim 68, wherein other NOR strings outside of the selected plurality of NOR strings are disconnected from circuitry at the surface of the semiconductor substrate during the read operation.

70. The memory circuit of claim 68, wherein the selected group of thin-film transistors are non-volatile or quasi-volatile.

71. The memory circuit of claim 70, further comprising one or more contacts provided to connect selectively the shared drain region of each NOR string through selection decoders to circuitry at the surface of the substrate.

72. The memory circuit of claim 71, wherein the selection decoders are disconnected from the contacts upon the shared drain regions being charged to a sense voltage.

73. The memory circuit of claim 71 wherein, during a read operation, the intrinsic capacitor of the source region of each NOR string is charged to a virtual ground voltage and an intrinsic capacitor of the drain region is charged to a read-sensing voltage,

74. The memory circuit of claim 73, wherein a selected one of the plurality of conductors is raised to sense to predetermined voltages to sense the threshold voltage of the thin-film storage transistor corresponding to the selected, raised conductor, while all other thin-film selected transistors on the selected NOR string are held at a non-conducting state.

75. The memory circuit of claim 71 wherein, during a programming operation, intrinsic capacitors of the source region, the drain region and the channel region of a selected thin-film storing transistor are each momentarily pre-charged to a virtual ground voltage.

76. The memory circuit of claim 75, wherein one or more programming voltage pulses are applied to corresponding one of the first plurality of conductors to initiate efficient Fowler-Nordheim tunneling or direct tunneling of charge from the source, drain and channel regions to the charge-trapping material, while all other ones of the first plurality of conductors are held at a voltage that inhibits initiation of efficient Fowler-Nordheim tunneling or direct tunneling of charge from the corresponding source, drain and channel regions to the charge-trapping material

77. The memory circuit of claim 76, wherein the programming operation is interrupted after a predetermined time and a program-verify read operation is carried out on the selected thin-film transistor.

78. The memory circuit of claim 77, wherein upon verification that the selected thin-film storage transistor is correctly programmed, the intrinsic capacitors of the source, drain and channel regions are charged to a program-inhibit voltage to prevent further programming, while continuing to apply the programming voltage pulses to the selected conductor until thin-film storage transistors on other NOR strings that share the selected conductor are verified to be correctly programmed.

79. The memory circuit of claim 71, wherein the contacts each comprise a buried contact.

80. The memory circuit of claim 79, wherein one or more pillars connect to channel regions of the thin-film transistors of a NOR string to circuitry at the surface of the substrate to provides a back-bias voltage or an erase voltage.

81. The memory circuit of claim 80, wherein all thin-film storage transistors of all NOR strings in one or more blocks of the memory circuit are erased in a single operation by applying one or more erase voltage pulses to the pillars, while holding the conductors in the first plurality of conductors at ground potential.

82. The memory circuit of claim 81, wherein a channel length of a selected thin-film transistor of the memory circuit is sufficiently short to assist the erase of programmed transistors by lateral hopping conduction and tunneling of stored charge out of the charge storage material into the corresponding source, drain and channel regions due to fringing electric field conditions between the corresponding one of the first plurality of conductors and corresponding source, drain and channel regions of the selected thin-film transistor.

83. The memory circuit of claim 82, wherein adjacent NOR strings are formed on opposite sides of an active strip and wherein only the thin-film storage transistors of one of the adjacent NOR strings is programmed for a read, program, or program-inhibit operation, while the thin-film storage transistors of the other one of the adjacent NOR strings are deactivated.

84. The memory circuit of claim 83, wherein an odd address is assigned to each thin-film transistor of a NOR string formed on one side of each active string and an even address is assigned to each thin-film transistor of a NOR string formed on the other side of the active string, wherein each of the first plurality of conductors is shared by a NOR string of an even address and a NOR string of an odd address, and wherein both the odd and even addressed NOR strings of active strips sharing the selected conductors are read, programmed, program-inhibited or erased concurrently by having their intrinsic capacitors of the shared source region, shared drain region and individual channel regions of the thin-film transistors of the NOR strings individually and independently of each other charged.

85. The memory circuit of claim 84, further comprising one or more reference strings set to one or more reference threshold levels to facilitate correctly program, erase and read the NOR strings.

86. The memory circuit of claim 85, wherein the intrinsic capacitors of both the shared source region and the share drain region of an active strip has substantially equal capacitance.

87. The memory circuit of claim 68, wherein (i) a second selected plurality of NOR strings are designated reference NOR strings, (ii) each sense amplifier comprises a differential sense amplifier and (iii) each sensing amplifier compares a signal received from its corresponding selected NOR string and a signal from one of the reference NOR strings.

88. The memory circuit of claim 87, wherein each reference NOR string is associated with more than one of the selected NOR strings.

89. The memory circuit of claim 87, wherein each reference NOR string is associated with exactly one of the selected NOR strings.

90. The memory circuit of claim 89, both the selected NOR string and the reference NOR string have approximately the same leakage current between their respective second and third semiconductor sublayers.

91. The memory circuit of claim 89, wherein the the reference NOR strings share the same plane as the selected NOR string.

92. The memory circuit of claim 87, wherein one or more of the thin-film storage transistors of the reference NOR string are programmed to have set reference threshold voltages that are used to correctly program and correctly read the threshold voltages of the selected NOR string.

93. The memory circuit of claim 87, further comprising a second plurality of conductors formed between the planar surface and the active strips along the first direction, the second plurality of conductors each connecting a portion of the circuitry at the surface of the semiconductor substrate to selected ones of the first plurality of conductors, wherein selected ones of the thin-film transistors in the reference NOR string are programmed to have set reference threshold voltages that are used to correctly program and correctly read the threshold voltages of corresponding thin-film storage transistors of the selected NOR string.

94. The memory circuit of claim 93, wherein the designated reference NOR strings are formed on the same plane (“

reference plane”

).

95. The memory circuit of claim 94, wherein each thin-film storage transistor in the selected NOR string and the corresponding thin-film transistor in the reference NOR string share one of the second plurality of conductors.

96. The memory circuit of claim 93, wherein thin-film storage transistors in a selected page in the reference plane and corresponding thin-film storage transistors in a page to which the selected NOR string belongs share corresponding ones of the second plurality of conductors.

97. The memory circuit of claim 96, wherein signals from thin-film storage transistors in a selected page in the reference plane and signals from corresponding thin-film storage transistors in a page to which the selected NOR string belongs are sensed in the corresponding sense amplifiers in the circuitry at the surface of the semiconductor substrate.

98. The memory circuit of claim 97, wherein the sense amplifiers are one set in a plurality of sets of sense amplifiers also connected to the selected page in the reference page and wherein all sense amplifiers in the plurality of sets of sense amplifiers operate simultaneously.

99. The memory circuit of claim 93, wherein one or more NOR strings in the reference plane are designated spare NOR strings, each spare NOR string being configurable to replace a NOR string outside of the reference plane.

101. The memory circuit of claim 87, wherein each reference NOR string provides a set of reference voltages used for programming and reading operations under a multi-bit scheme.

102. The memory circuit of claim 87, wherein each reference NOR string provides a continuum of reference voltages to be used for programming and reading analog voltage states.

103. The memory circuit of claim 87, wherein each reference NOR string provides a continuum of reference voltages to be used for programming and reading under a multi-bit scheme.

104. The memory circuit of the claim 87, wherein the circuitry at the surface of the semiconductor substrate provides the source and drain regions of thin-film storage transistors of the reference NOR string successively a range of voltages to be used for detecting the programmed voltage stored on the corresponding thin-film storage transistors in the sleected NOR string.

105. The memory circuit of claim 47, wherein one or more spare NOR strings is provided in each plane for replacing any one of a plurality of NOR strings in the same plane.

106. The memory circuit of claim 47, wherein one or more of the planes is designated a redundant plane, the redundant planes providing spare NOR strings for replacing NOR strings in the other planes, or for replacing pages on the other planes.

107. The memory circuit of claim 47, wherein each thin-film storage transistor in a reference NOR string is programmed to provide a first reference voltage, and wherein, during a programming or reading operation, the circuitry at the surface of the semiconductor substrate raises the voltages at the shared source and drain regions of that thin-film storage transistor in the reference NOR string according to a set or a continuum of additional reference voltages, so as to provide correct programming and reading voltages to corresponding thin-film storage transistors in the selected NOR string under a multi-bit or analog data scheme.

108. The memory circuit of claim 107, wherein the leakage current in the reference NOR string and the leakage current in the selected NOR string are matched by modulating the voltages on the common source region and the common drain region of thin-film storage transistors in the reference string.

109. The memory circuit of claim 108, further comprising a second plurality of conductors formed between the planar surface and the active strips along the first direction, the second plurality of conductors each connecting a portion of the circuitry at the surface of the semiconductor substrate to selected ones of the first plurality of conductors, wherein one or more of the second plurality of conductor and its associated thin-film storage transistors in the reference NOR string is dedicated for matching the leakage currents.

110. The memory circuit of claim 109, wherein reference threshold voltages corresponding to programmed states under a multi-bit scheme are stored in separate reference NOR strings.

111. The memory circuit of claim 87, wherein the reference NOR strings are rotated sequentially or randomly according to a rotation scheme, so as to match degradation in the selected NOR strings resulting from extended program/erase cycling.

112. The memory circuit of claim 111, wherein assigned addresses of the thin-film transistors of the reference NOR strings are updated after each rotation and stored within the memory circuit or outside the memory circuit.

113. The memory circuit of claim 61, wherein each active strip comprises one or two NOR string wherein, during a read or program operation of a selected thin-film storage transistor, only the corresponding one of the first plurality of conductors adjacent the selected thin-film storage transistor is momentarily raised to the predetermined voltage required for the read or program operation, with the corresponding ones of the first plurality of conductors associated with all other thin-film storage transistors in the NOR string held at a voltage below a threshold voltage of an erased storage element.

114. memory circuit of claim 61, wherein within a column of active strips, active strips not having a thin-film transistor selected for a read or programmed operation have their intrinsic capacitor charged to an inhibit voltage.

115. The memory circuit of claim 61, wherein multiple thin-film transistors associated with active strips within a column are programmed in a single concurrent programming operation.

116. The memory circuit of claim 61 wherein, during a concurrent programming operation, the intrinsic capacitor of each active strip in each plane is charged to a predetermined voltage associated with a program or program-inhibit operation, a programming voltage to then apply to addressed ones of the first plurality of conductors associated with each active strip, and wherein the concurrent programming operation is terminated after all thin-film storage transistors associated with the addressed ones of the first plurality of conductors are verified to have reached their respective intended states.

117. The memory circuit of claim 116, wherein the programming voltage applied to each of he addressed ones of the first plurality of conductors is one of several programming voltages in a programming sequence, each of the programming voltages representing a different data value.

118. The memory circuit of claim 61, wherein the intrinsic capacitor of each active strip in one or more planes is concurrently charged to a predetermined voltage associated with a read operation prior to carrying out the read operation with the charged intrinsic capacitors providing local voltage sources..

119. The memory circuit of claim 118, wherein the charged intrinsic capacitors are refreshed in the background in a standby mode or charging is initiated for selected blocks in anticipation of impending read operations, so as to allow fast subsequent concurrent read or fast subsequent random accessed read of thin-film storage transistors in one or more pages on one or more planes.

120. The memory circuit of claim 118, wherein the local voltage sources are isolated from each other and from the circuitry at the surface of the substrate, such that ground bounce is avoided when the addressed thin-film storage transistors are concurrently read.

121. The memory circuit of claim 61 wherein, during an erase operation, a voltage on the intrinsic capacitor of each active strip imposed from the circuitry at the surface of the substrate is further boosted to a predetermined erase voltage by raising a voltage on all unselected ones of the first plurality of conductors, while keeping a voltage on corresponding ones of the first plurality of conductors that are selected for erase at another predetermined voltage.

122. The memory circuit of claim 61, wherein each active strip comprises a first NOR string formed along one side of the active strip and a second NOR string formed along the other side of the active strip, wherein, one of the first plurality of conductors is located between the first NOR string of a first active strip and the second NOR string of a second active strip, and wherein the intrinsic capacitor of the first NOR string of the first active strip is charged to programming voltage, while the intrinsic capacitor of the second active strip is charged to a program-inhibit voltage.

123. The memory circuit of claim 122, wherein that one of the conductors is applied pulses of one or more programming voltages or a ramp of successively higher programming voltage pulses.

124. The memory circuit of claim 123, wherein the pulses of programming voltages are successively higher and, between the pulses of programming voltages, the thin-film storage transistor associated with that one of the conductors is read.

125. The memory circuit of claim 124 wherein the pulses of programming voltages is stopped when reading the thin-film storage transistor indicates that it has been programmed to its intended threshold voltage and wherein, thereafter, the intrinsic capacitor of the first NOR string is charged to a predetermined program-inhibit voltage.

126. The memory circuit of claim 125, wherein each pulse of the programming voltages corresponds to a threshold voltage in the thin-film storage transistor under a multi-bit storage scheme.

127. The memory circuit of claim 122, wherein the intrinsic capacitor of the first NOR string of the first active strip is charged to a program-inhibit voltage upon read-verification that a selected one of the thin-film storage transistor associated with that one of the first plurality of conductors is in their correctly programmed state.

128. The memory circuit of claim 61 wherein, during a programming operation of a selected thin-film storage transistor in each of a selected plurality of NOR strings, the selected group of thin-film storage transistors in each of the selected NOR strings charge the intrinsic capacitor of the floating one of the second and third semiconductor sublayers of the NOR string successively to one of a plurality of predetermined voltages from the circuitry at the surface of the semiconductor substrate, each predetermined voltage being one of a plurality of intended threshold voltage states for the selected thin-film storage transistors.

129. The memory circuit of claim 1, wherein the first semiconductor sublayer in each active strip is formed subsequent in time to all second and third sublayers of all active strips are formed.

130. The memory circuit of claim 61, wherein the thin-film storage transistors used to charge the intrinsic capacitor are not used for data storage.

131. The memory circuit of claim 63, wherein multiple selected active strips on one or more planes on one or more blocks are appropriately charged to provide the local current sources of these multiple selected active strips so as to allow concurrent or sequential programming or program-inhibition or erase operations in parallel.

132. The memory circuit of claim 63, wherein selected thin-film storage transistors in active strips within a page are programmed, program-inhibited, or read concurrently.

133. The memory circuit of claim 63, wherein selected thin-film storage transistors that are within a slice are programmed, program-inhibited, read or erased concurrently.

134. The memory circuit of claim 63, wherein each thin-film storage transistor stores more than one bit of binary information.

135. The memory circuit of claim 63, wherein said data represents a continuum of stored states in an analog memory.

136. The memory circuit of claim 63, wherein the circuitry further comprise one or more sense amplifiers for sensing data stored in the thin-film storage transistors.

137. The memory circuit of claim 63, further comprising one or more sense amplifiers for concurrently reading the data stored in selected thin-film storage transistors from one or more pages in a slice.

138. The memory circuit of claim 63, wherein the intrinsic capacitors of multiple active strips on one or more planes in one or more selected blocks are charged to predetermined voltage conditions prior to thin-film storage transistors associated with the multiple active strips are read concurrently.

139. The memory circuit of claim 63, wherein the intrinsic capacitors of multiple active strips on one or more planes in one or more selected blocks are charged to predetermined voltage conditions prior to thin-film storage transistors associated with the multiple active strips are read sequentially.

140. The memory circuit of claim 4, wherein the thin-film storage transistors are read-refreshed and program-refreshed at time intervals less than a predetermined time period.

141. memory circuit of claim 140, wherein the predetermined time period is determined based on margin-read conditions.

142. The memory circuit of claim 141, wherein the circuitry at the surface of the semiconductor substrate comprise a data integrity detection circuit.

143. The memory circuit of claim 141, wherein the circuitry at the surface of the semiconductor substrate comprises a data parity circuit.

144. The memory circuit of claim 141, wherein the circuitry at the surface of the semiconductor substrate comprises an error correcting circuit.

145. The memory circuit of claim 141, wherein the circuitry at the surface of the substrate comprises a first set of one or more input/output ports for communicating with an external system controller and a second set of one or more input/output ports for communicating data read from and written into the thin-film storage transistors.

146. The memory circuit of claim 142, wherein the data integrity circuit, upon detecting an error, communicate the error to the external system controller, thereby enabling the external system controller to carry out a data recovery and program-refresh operation.

147. memory circuit of claim 142, wherein the circuitry at the surface of the semiconductor substrate comprises interface circuits that allows direct access to the second set of input/output ports for random access to the thin-film storage transistors under one or more conventional DRAM, SRAM, NOR flash word-wide protocols.

148. The memory circuit of claim 147, wherein one of the second set of input/output ports implements a serial data streaming protocol.

149. The memory circuit of claim 141, wherein the external controller provides a value for the time predetermined time period.

150. The memory circuit of claim 149, wherein the value tracks a program/erase cycle count or a sense temperature for the memory circuit.

151. The memory circuit of claim 141 wherein the memory circuit performs a read-refresh or program-refresh operation on a portion of the thin-film storage transistors in a background mode, while carrying out concurrently read, program, or erase operations in a second portion of the thin-film storage transistors and powering down a third portion of the thin-film storage transistors.

152. The memory circuit of claim 151, wherein, the memory circuit allows the external system controller to initiate a temporary interrupt of the read-refresh or program-refresh operation to allow a read access to the first portion of thin-film storage transistors.

153. The memory circuit of claim 141, wherein the charge-trapping material has a tunneling dielectric layer sufficiently thin to initiate direct tunneling of charge from the first semiconductor sublayer into the charge-trapping layer.

154. The memory circuit of claim 151, wherein the tunneling dielectric layer is no greater than 3 nanometers thick.

155. The memory circuit of claim 151, wherein the electric charge is provided from the first semiconductor sublayer through Fowler-Nordheim tunneling mechanism.

156. The memory circuit of claim 135 wherein each thin film transistor has a threshold voltage window between an erased state and a programmed state that is no greater than 2 volts.

157. The memory circuit of claim 61, wherein each active strip comprises a first NOR string formed along one side of the active strip and a second NOR string formed along the other side of the active strip, wherein, one of the first plurality of conductors is located between the first NOR string of a first active strip and the second NOR string on a second active strip, and wherein thin-film storage transistors in the first NOR string of the first active strip serve as a reference transistors for corresponding thin-film transistors in the second NOR string of the second active strip forming a related transistor pairs, one of the thin-film transistor of the related transistor pair serving in a reference transistor role to the other transistor in the related transistor pair, wherein the reference transistor holds the programmed state while the other of the related transistor pair holds the erased state, and vice versa, and wherein output signals from the thin-film storage transistors of the related transistor pair are fed simultaneously into a differential sense amplifier to determines the data represented by the output signals.

158. The memory circuit of claim 157, wherein both thin-film storage transistors of the related transistor pair are erased prior to programming.

159. The memory circuit of claim 157, the thin-film transistors in the related transistor pair reverses roles in successive programming operations to substantially equalize cumulative degradations.

160. The memory circuit of claim 157, further comprising a second plurality of conductors formed between the planar surface and the active strips along the first direction, the second plurality of conductors each connecting a portion of the circuitry at the surface of the semiconductor substrate to selected ones of the first plurality of conductors, wherein thin-film storage transistors in one or more pages or slices sharing one of the second plurality of conductors and which are physically within a predetermined distance from the circuitry at the surface of the semiconductor substrate are configured to operate as related transistor pairs (“

high speed configuration”

).

161. The memory circuit of claim 160, wherein the remainder of the pages or slices are configured to operate with one reference transistor for two or more thin-film storage transistors (“

low cost configuration”

) within the pages or slices.

162. The memory circuit of claim 161, wherein one or more planes of the memory circuit operate in the high-speed memory, while other planes of the memory circuit operate in the low cost configuration.

163. The memory circuit of claim 161, wherein one or more blocks of the memory circuit operate in the high-speed configuration, while other blocks of the memory circuit operate in the low cost configuration.

164. The memory circuit of claim 161 wherein, under the low cost configuration, more than one binary bit of information is stored in each thin-film storage transistor and wherein more than one reference NOR string is provided to read the stored mult-ibit information.

165. The memory circuit of claim 164, wherein the thin-film storage transistors operating under the high-speed configuration store on-chip resource management data for use by an external controller.

166. The memory circuit of claim 165, wherein the on-chip resource management data includes an updatable file allocation table for files stored in the memory circuit.

167. The memory circuit of claim 166, further comprising a unique identifier index number and a time-stamp that is appended to each stored data file when it is updated.

168. The memory circuit of claim 167, wherein each file having an entry of the file allocation table includes status information related to the file for an external system controller.

169. memory circuit of claim 168, wherein the status information includes two or more of;

delete file, move file to cold storage, move file to archival storage, defective file, skip-over file, and address of substitute file.

170. The memory circuit of claim 168, wherein the circuitry at the surface of the semiconductor substrate comprises circuitry for search simultaneously one or more file allocation tables for a file identifier broadcasted by the external system controller.

171. The memory circuit of claim 161, wherein one or more selected pages within a selected slice have their intrinsic capacitors charged to a programming voltage, while other pages within the selected slice have their intrinsic capacitors charged to a program-inhibit voltage, wherein conductors within the second plurality of conductors corresponding to slices outside of the selected slice are held at a ground voltage.

172. The memory circuit of claim 161, wherein one or more selected blocks are erased in a single erase operation, or one or more selected slices within the blocks are erased, in a single operation, while inhibiting erase in all other slices within the blocks.

173. The memory circuit claim 172, wherein the erase operation is followed by a read-verify operation and a soft-programming operation which restores the thin-film storage transistors of the erased slices or blocks back to an enhancement threshold voltage.

174. The memory circuit of claim 161, wherein one or more selected pages within a selected slice are charged for a read operation, while conductor of the second plurality of conductors not associated with the selected slice are held in the “

off”

state.

175. The memory circuit of claim 161, wherein each NOR string along one of an active strip is operated as an independently addressable NOR string of multiple side-by-side variable threshold thin-film storage transistors.

176. The memory circuit of claim 175, wherein each NOR string is provided decoded access to the circuitry at the surface of the semiconductor substrate to receive voltages for erase, program and program-inhibit operation, virtual source ground voltage, and a drain voltage during read-sensing by sense amplifiers.

177. The memory circuit of claim 176, wherein each NOR string is provided decoded access to a substrate back-bias voltage during read, program, or erase operation.

178. The memory circuit of claim 174, wherein the circuitry at the surface of the substrate further comprises a pipeline streaming circuitry that overlaps sensing a page of data of a file in sense amplifiers and transferring the sensed data to a data buffer for serial bit stream, or parallel word-wide output from the memory circuit, with concurrently reading a next page of the file from the memory circuit for sensing in the sense amplifies.

179. The memory circuit of claim 178, wherein the overlap covers time required for charging the intrinsic capacitors associated with reading the next page of the file.

180. The memory circuit of claim 179, wherein the data buffer is provided within a portion of the memory circuit operating under the high speed configuration, while the next page of the file is being read from a portion of the memory circuit operating under low cost configuration.

181. The memory circuit of claim 180, wherein one or more data files are read concurrently and their data streams are routed to one or more data input/output ports of the memory circuit.

182. The memory circuit of claim 181, wherein the data input/output ports comprise a high-speed word-wide memory interface implementing one or more of DRAM, SRAM, NOR XIP, and high-speed serial streaming protocols.

183. The memory circuit of claim 181, wherein the data input/output ports comprise a data interface implementing one or more of PCIe, NVMe, SATA, SAS, USB, SD, eMMC and other data transfer protocols.

184. The memory circuit of claim 4, wherein the first semiconductor sublayer is provided in cavities arisen after removal of a sacrificial layer.

185. The memory circuit of claim 184, wherein the first semiconductor sublayer has a width that is independent of the widths of the second and third semiconductor sublayers.

186. The memory circuit of claim 184, wherein the first semiconductor sublayer of each active strip is substantially the same for all active strips aligned along the second direction.

187. The memory circuit of claim 184, wherein the first semiconductor sublayer has a thickness that is sufficiently thin to be readily depleted when appropriate voltage is applied between the conductors and the second and third semiconductor sublayers.

188. The memory circuit of claim 184, wherein the channel region of each thin-film storage transistor has a length substantially determined by a thickness of the sacrificial layer removed.

189. The memory circuit of claim 184, wherein the channel region of each thin-film has a length that is sufficiently short to accelerate the erase operation by removal of charge trapped in the charge-trapping material adjacent the channel region, assisted by fringing-field-aided lateral hopping conduction of charge within the charge-trapping layer, when an appropriate voltage is applied between the gate terminal and the source and drain regions during the erase operation.

190. The memory circuit of claim 189, wherein the length is between 5 and 50 nanometers.

100. The memory circuit of 93, wherein one or more slices are designated reference slices for the other slices in the memory circuit and wherein one or more of the thin-film storage transistors of each reference slice are programmed to have set reference threshold voltages that are used to correctly program and correctly read the threshold voltages of corresponding thin-film storage transistors in the other slices.

191. A semiconductor manufacturing process for three-dimensional memory blocks, comprising:

providing a semiconductor substrate and forming circuitry therein and thereon;

forming a first set of low resistivity conductor wirings above the semiconductor substrate and connected to the circuitry through via openings;

depositing and planarizing a first isolation layer;

forming a first set of buried contacts in the first isolation layer to provide electrical connections to the circuitry in the semiconductor substrate;

forming over the first isolation layer a first plane of semiconductor material, the first plane of semiconductor material comprising second and third semiconductor sublayers of a first conductivity type, separated from each other by a layer of a first sacrificial material, wherein the first set of buried contacts provide electrical contact between one or more of the second and third semiconductor sublayers and the circuitry in the semiconductor substrate;

patterning and removing portions of the first plane of semiconductor material to make room for a next set of the buried contacts;

repeating for a predetermined number of times the steps of (i) depositing an additional isolation layer;

(ii) forming that next set of buried contacts to provide electrical connections to the circuitry in the semiconductor substrate;

(iii) forming over the additional isolation layer to provide an additional plane of semiconductor material, comprising second and third semiconductor sublayers of the first conductivity type, separated from each other by a layer of the first sacrificial material, wherein one or more of the second and third semiconductor sublayers of the additional plane of semiconductor are electrically contacted by one of that next set of buried contacts; and

(iv) patterning and removing portions of the additional plane of semiconductor material to provide room for another next set of the buried contacts; and

patterning and anisotropically etching the isolation layers and the planes of semiconductor materials to form an array of active strips.

192. The process of claim 191, further comprising annealing the first plane and each of the additional planes of semiconductor material to activate dopants in the second and third semiconductor sublayers.

193. The process of claim 192, wherein the annealing is performed simultaneously for all planes of semiconductor material.

194. The process of claim 193, wherein the annealing is performed either by rapid thermal annealing or by laser annealing.

195. The process of claim 192, wherein the annealing is performed individually for each plane of semiconductor material using shallow annealing by excimer laser.

196. The process of claim 191, wherein the patterning and anisotropically etching of the first isolation layer, the first plane of semiconductor material, the additional isolation layers and the additional planes of semiconductor materials are performed using a hard mask.

197. The process of claim 191, wherein the array of active strips comprises a plurality of stacks of active strips, each stack being separated from an adjacent stack by one of a first set of trenches having sidewalls running lengthwise in a first direction that is substantially parallel to a surface of the semiconductor substrate.

198. The process of claim 197, further comprising filling the trenches between the stacks of active strips using a second sacrificial material.

199. The process of claim 198, further comprising:

forming a second set of trenches through the second sacrificial material to expose portions of one or both sidewalls of each stack of active strips; and

removing at least a portion of the first sacrificial material from all active strips, wherein the removing is performed using an etchant that selectively removes the first sacrificial material without materially etching the second and third semiconductor sublayers in each active strip or the second sacrificial material and wherein the removing forms cavities between the second third layers of semiconductor sublayers in each active strip.

200. The process of claim 199, further comprising depositing a first semiconductor sublayer of a second conductivity type inside the cavities and conformal with sidewalls of the second set of trenches, and removing the second sacrificial material to expose additional sidewall surfaces of the stacks of active strips.

201. The process of claim 200, further comprising forming a charge-storage layer conformal with the exposed sidewalls of the stacks of active strips and extending over the bottom of each of first set of trenches exposed by removing the second sacrificial material.

202. The process of claim 201, wherein the charge-storage layer comprises one or more layers of charge-trapping material selected form silicon nitride, silicon-rich silicon nitride, silicon oxide, nanocrystals, nanodots embedded in a thin dielectric film, or isolated floating gates, wherein each layer of charge-trapping material being provided between one or more layers of a dielectric material selected from the group consisting of silicon oxide, high dielectric-constant films of aluminum oxide or hafnium oxide, and bandgap engineered dielectrics.

203. The process of claim 202, wherein each layer of charge-trapping material is 4-12 nm thick.

204. The process of claim 202, wherein the charge-storage layer further comprises a 5-15 nm blocking dielectric film selected from an ONO layer, a high dielectric constant film of materials including aluminum oxide, hafnium oxide or some combination thereof

205. The process of claim 201, wherein the charge storage layer further comprises a tunnel dielectric film of 2-10 nm thick that is formed by chemical or atomic layer deposition, or oxidation of silicon oxide, silicon nitride or a band gap-engineered dielectric sandwich.

206. The process of claim 205, wherein the tunnel dielectric layer is 3 nm or less thick and is formed by chemically depositing or growing a silicon dioxide layer, a silicon oxide-silicon nitride-silicon oxide (“

ONO”

) triple layer, a bandgap engineered dielectric or a silicon nitride layer.

207. The process of claim 201, further comprising:

providing in the first set of trenches a conductive material adjacent the exposed charge-storage layer; and

patterning and etching the conductive material to form a plurality of conductors that extend lengthwise along the second direction.

208. The process of claim 207, further comprising:

providing a dielectric layer over the stacks of active strips and the conductors;

forming openings in the dielectric for electrically contacting the conductors in the first set of trenches; and

providing a second set of low resistivity conductor wirings over the dielectric layers, the second set of low resistivity conductor wirings making electrical contact with the conductors through the openings in the dielectric layer.

209. The process of claim 208, wherein one or more of the second and third semiconductor sublayers of each active strip are connected to the second set of low resistivity conductor wirings through the openings in the dielectric layer provided as a set of stepped staircase vias.

210. The process of claim 208, further comprising, prior to providing in the first set of trenches the conductive material, removing the charge-storing layer from at least each alternate bottom of the first set of trenches to expose openings for electrical contact to the first set of low resistivity conductor wirings, and wherein the openings in the dielectric layer is provided only to conductors without electrical contacts to the first set of low resistivity wirings.

211. The process of claim 201, wherein only selected ones of the first set of trenches are provided the charge-storage layer, and wherein removing the first sacrificial material is performed after the charge-storage layer are formed, such that the sidewalls of the first set of trenches not covered by the charge-storage layer provides back-side access to removal of the first sacrificial material.

212. The process of claim 197, further comprising:

controlled sideway etching to remove at least a portion of the first sacrificial material to form recesses in one or both side edges of each active strips, the recesses from each side of the active strip being separated from each other by the remainder of the first sacrificial material in the active strip; and

depositing semiconductor material of a second conductivity type to form a first semiconductor sublayer in the recesses and conformal over the sidewalls of the first set of trenches.

213. The process of claim 212, further comprising removing the semiconductor material from the sidewalls of the first set of trenches without removing the semiconductor material in the recesses.

214. The process of claim 212, further comprising, prior to depositing the semiconductor material, providing a dopant diffusion-blocking layer over the sidewalls of the recesses.

215. The process of claim 214, wherein the dopant diffusion-blocking layer is provided by chemical or atomic layer deposition or by thermal growth and has a thickness between one atomic layer and three nanometers.

216. The process of claim 214, wherein the dopant diffusion-blocking material comprises an oxide, a nitride of silicon, or silicon-germanium.

217. process of claim 214, further comprising oxidizing partially or in total exposed side edges of the dopant diffusion-blocking layer to form a silicon dioxide layer.

218. The process of claim 214, further comprising forming a silicon oxide-silicon nitride-silicon oxide (“

ONO”

) triple layer over exposed side edges of the dopant diffusion-blocking layer.

219. The process of claim 215, wherein the second and third semiconductor sublayers each comprise amorphous or polycrystalline silicon and the first semiconductor sublayer comprises amorphous silicon, recrystallized silicon, polycrystalline silicon, or silicon-germanium.

220. The process of claim 219, wherein one or both of the second and third semiconductor sublayers are doped in-situ or ion implanted to have the second conductivity.

221. The process of claim 220, wherein the dopant concentration in each of the second and third semiconductor sublayers is in the range of 1×

10¹⁹ and 1×

10²¹ dopants per cm³.

222. The process of claim 219, wherein the first semiconductor sublayer is deposited undoped, in-situ doped or diffusion doped, and wherein the first, second and third semiconductor sublayers in the planes of semiconductor material are exposed to rapid thermal annealing to activate the dopants and to recrystallize the semiconductor material.

223. The process of claim 222, wherein the dopant concentration of the first semiconductor sublayer is in the range between native and 1×

10¹⁸ dopants per cm³.

224. The process of claim 207, wherein the conductors comprise in-situ doped N⁺ polysilicon, P⁺ doped polysilicon, a silicide or polycide, or a refractory metal of reasonably high metal work function with respect to silicon oxide.

225. The process of claim 191, further comprising providing in each plane of semiconductor material a low resistivity metallic or silicide sublayer that is in contact with one or both of the second and third semiconductor sublayers.

226. The process of claim 191, further comprising providing in each plane of semiconductor material a dopant diffusion-blocking sublayer that is in contact with one or both of the second and third semiconductor sublayers.

227. The process of claim 207, further comprising removing a portion of the charge-storage along the sidewalls of the trenches in areas located between conductors.

228. The process of claim 205, further comprising etching a portion of the charge-storage layer at the isolation layers between the active strips.

229. The process of claim 228, wherein, the etching further etches a portion of the tunnel dielectric layer in the charge-storage layer from a back surface of the charge-storage material.

230. The process of claim 201, wherein the charge-storage layer is provided a thickness such that electric charge from the first, second and third semiconductor sublayers tunnel into the charge-storage layer through Fowler-Nordheim tunneling under a predetermined range of electric fields.

231. The process of claim 205, wherein the tunnel dielectric layer of the charge storage material is adapted to have a thickness such that electric charge from the first, second and third semiconductor sublayers tunnel into the charge-storage layer through direct tunneling under a predetermined range of electric fields.

232. The process of claim 205, wherein the tunnel dielectric layer is provided to have a thickness such that electrons from the first, second and third semiconductor sublayers are injected into the charge-storage by channel hot-electron injection under a predetermined range of electric fields when a current flows in the semiconductor sublayer.

233. The process of claim 191, wherein the second and third semiconductor sublayers of a first conductivity type is provided by:

providing layers of a third sacrificial material to sandwich the first sacrificial layer;

removing the third sacrificial material to form cavities; and

filing the cavities with semiconductor material to form the second and third semiconductor sublayers.

234. A semiconductor manufacturing process for three-dimensional memory blocks, comprising:

providing a semiconductor substrate and forming circuitry therein and thereon;

forming a first set of low resistivity conductor wirings above the semiconductor substrate and connected to the circuitry through via openings;

depositing and planarizing a first isolation layer;

forming a first set of buried contacts in the first isolation layer to provide electrical connections to the circuitry in the semiconductor substrate;

forming over the first isolation layer a first plane of semiconductor material, the first plane of semiconductor material comprising second and third semiconductor sublayers of a first conductivity type, separated from each other by a layer of a first sacrificial material, wherein the first set of buried contacts provide electrical contact between one or more of the second and third semiconductor sublayers and the circuitry in the semiconductor substrate;

patterning and removing portions of the first plane of semiconductor material to make room for a next set of the buried contacts;

repeating for a predetermined number of times the steps of (i) depositing an additional isolation layer;

(ii) forming that next set of buried contacts to provide electrical connections to the circuitry in the semiconductor substrate;

(iii) forming over the additional isolation layer to provide an additional plane of semiconductor material, comprising second and third semiconductor sublayers of the first conductivity type, separated from each other by a layer of the first sacrificial material, wherein one or more of the second and third semiconductor sublayers of the additional plane of semiconductor are electrically contacted by one of that next set of buried contacts; and

(iv) patterning and removing portions of the additional plane of semiconductor material to provide room for another next set of the buried contacts; and

patterning and anisotropically etching the isolation layers and the planes of semiconductor materials to form an array of active stripsdepositing and planarizing a first isolation layer;

patterning and anisotropically etching isolation layers and the planes of semiconductor material to form an array of active strips, the array of active strips comprising a plurality of stacks of active strips, each stack being separated from an adjacent stack by one of a first set of trenches having sidewalls running lengthwise along a first direction that is substantially parallel to a surface of the semiconductor substrate;

forming a charge-storage layer conformal with the exposed sidewalls of the stacks of active strips;

patterning and etching openings in the charge-storage layer to expose areas in one or both the sidewalls of each stack of active strips;

selectively etching the first sacrificial material in each active strip from the exposed sidewalls to form one or more cavities between the second and third semiconductor sublayers; and

depositing semiconductor material in the cavities and in selected portions of the exposed ones of the first set of trenches to form a first semiconductor sublayer and pillars of semiconductor material in the exposed ones of the first set of trenches.

235. The process of claim 234, wherein the isolation layers separating adjacent planes of semiconductor materials are etched to create air gaps that lessen parasitic capacitive coupling between the active strips.

236. The process of claim 234, wherein the pillars of semiconductor material partially wrapped around the active strips in each stack to electrically shield between proximate active strips.

237. The process of claim 236, wherein the pillars of semiconductor material connect the first sublayers of each active strip to circuitry in the semiconductor substrate.

238. The process of claim 237, further comprising etching away the pillars of semiconductor material without removing the first semiconductor sublayer.

239. The process of claim 234, wherein selectively etching the first sacrificial material is performed using an etchant that does not materially etch the charge-storage layer, the isolation layers and the second and third sublayers of the active planes.

240. A method for a system controller to rapidly determine the location of the most current version of a data file stored on one of many memory circuits,

in each memory circuit:

(a) associating a first page of the data file with a unique identifier index number generated by the system controller and appending the unique identifier index number to the data file; and

(b) associating a time-stamp with the unique identifier index number every time the data file is stored in the memory circuit, wherein all unique identifier index numbers for all files stored in each memory circuit are stored in a lookup table in the memory circuit with the latest time-stamp and the location in the memory circuit at which the file is stored;

sending from the system controller a search request which is broadcast simultaneously to one or more of the memory circuits, the search request specifying unique identifier index number of the file to be located; and

using exclusive-or (XOR) circuits or content addressable memory (CAM) circuits in each memory circuit, simultaneously across some or all memory circuits, to compare the broadcasted unique identifier index number with the unique identifier index numbers stored in the look-up table of each memory circuit and reporting to the system controller when a match has been found along with its time-stamp and location, wherein when more than one match is found, the system controller selects from the reported locations the location whose associated time-stamp is the latest among the time-stamps reported.

241. The method of claim 240, wherein each memory circuit comprises a portion which is configured to operate as a low read-latency cache memory, and wherein the look-up table is stored in the cache memory.

242. A memory circuit, comprising:

a semiconductor substrate having a substantially planar surface and including circuitry formed therein and thereon; and

a dielectric layer formed over the planar surface of the semiconductor substrate; and

a semiconductor structure formed over the dielectric layer, comprising a first semiconductor sublayer of a first conductivity type provided between a second and a third semiconductor sublayers each of a second conductivity type, the first, the second and third semiconductor sublayers providing the semiconductor structure a sidewall;

a conductor substantially outside the semiconductor structure substantially aligned with a portion of the second semiconductor sublayer; and

a charge-storage layer provided over the sidewall of the semiconductor structure between the conductor and the aligned portion of the semiconductor sublayer, wherein the first, second and third semiconductor sublayers providing, respectively, channel, source and drain regions of a thin-film storage transistor, wherein the conductor provides a gate electrode to the thin-film storage transistor, and wherein one of the second and third semiconductor sublayers is electrically floating relative to the circuitry formed in the semiconductor substrate, except when the channel region is rendered conducting.

243. The memory circuit of claim 242, wherein the first semiconductor sublayer provides a covering layer that defines a portion of a cavity inside the semiconductor structure.

244. The memory circuit of claim 242, wherein a separation between the second and third semiconductor sublayers has a thickness substantially defined by a sacrificial material, and wherein the first semiconductor sublayer is provided after removal of at least a portion of the sacrificial material is removed from between the second and third semiconductor sublayers.

245. The memory circuit of claim 244, wherein a portion of the semiconductor material remains between the second and third semiconductor sublayers to provide mechanical support.

246. The memory circuit of claim 242, further comprising interconnect conductors embedded in the dielectic layer to interconnect the thin-film storage transistor and the circuitry at the planar surface of the semiconductor substrate.

247. The memory circuit of claim 246, further comprising buried contacts formed in the dielectric layer to electrically connect the other one of the second and third semiconductor sublayers.

248. The memory circuit of claim 242, further comprising a dopant diffusion-blocking layer between the first semiconductor sublayer and one or both of the second and the third semiconductor sublayer.

249. The memory circuit of claim 242, wherein the charge-storage layer comprises one or more layers of charge-trapping material selected form silicon nitride, silicon-rich silicon nitride, silicon oxide, nanocrystals, nanodots embedded in a thin dielectric film, or isolated floating gates, wherein each layer of charge-trapping material being provided between one or more layers of a dielectric material selected from the group consisting of silicon oxide, high dielectric-constant films of aluminum oxide or hafnium oxide, and bandgap engineered dielectrics.

250. The memory circuit of claim 249, wherein the charge-trapping layer further comprises a blocking dielectric film selected from an ONO layer, a high dielectric constant film of materials including aluminum oxide, hafnium oxide or some combination thereof

251. The memory circuit of claim 242, wherein the charge storage material comprises a tunnel dielectric film.

252. The memory circuit of claim 251, wherein the tunnel dielectric layer comprises one or more of a silicon dioxide layer, a silicon oxide-silicon nitride-silicon oxide (“

ONO”

) triple layer, a bandgap engineered dielectric and a silicon nitride layer.

253. A semiconductor manufacturing process for three-dimensional memory blocks, comprising:

providing a semiconductor substrate and forming circuitry therein and thereon;

forming a set of low resistivity conductor wirings above the semiconductor substrate and connected to the circuitry through via openings;

depositing and planarizing an isolation layer;

forming a set of buried contacts in the isolation layer to provide electrical connections to the semiconductor substrate and to the low resistivity conductor wirings;

forming over the isolation layer a first plane of semiconductor material, the first plane of semiconductor material comprising second and third semiconductor sublayers of a first conductivity type, separated from each other by a layer of a first sacrificial material, wherein the buried contacts are in electrical contact with one or more of the second and third semiconductor sublayers; and

patterning and anisotropically etching the isolation layer and the plane of semiconductor material to form an array of active strips.

254. The process of claim 253, further comprising annealing the plane of semiconductor material to activate dopants in the second and third semiconductor sublayers.

255. The process of claim 254, wherein the annealing is performed by rapid thermal annealing, by laser annealing or by shallow annealing by excimer laser.

256. The process of claim 254, further comprising removing at least a portion of the first sacrificial material using an etchant that selectively removes the first sacrificial material without materially etching the second and third semiconductor sublayers, wherein the removing form a cavity between the second third layers of semiconductor sublayers in each active strip.

257. The process of claim 256, further comprising depositing a first semiconductor sublayer of a second conductivity type inside the cavity.

258. The process of claim 253, further comprising forming a charge-storage layer conformal with the exposed sidewalls of the active strips.

259. The process of claim 258, wherein the charge storage material is formed by depositinor thermally growing a tunnel dielectric film.

260. The process of claim 253, further comprising:

controlled sideway etching to remove at least a portion of first sacrificial material to form recesses in one or both side edges of each active strips, the recesses from each side of the active strip being separated from each other by the remainder of the first sacrificial material in the active strip; and

depositing semiconductor material of a second conductivity type to form a first semiconductor sublayer in the recesses and conformal over the sidewalls of the first set of trenches.

261. The process of claim 259, further comprising, prior to depositing the semiconductor material, providing a dopant diffusion-blocking layer over the sidewalls of the recesses.

262. The process of claim 261, wherein the dopant diffusion-blocking layer is provided by chemical or atomic layer deposition or by thermal growth and has a thickness between one atomic layer and three nanometers.

263. The process of claim 253, further comprising providing in the plane of semiconductor material a dopant diffusion-blocking sublayer that is in contact with one or both of the second and third semiconductor sublayers.

264. The process of claim 258, further comprising:

providing a conductive material adjacent the exposed charge-storage layer; and

patterning and etching the conductive material to form a plurality of conductors that extend lengthwise along the second direction.

265. The process of claim 264, further comprising removing a portion of the charge-storage in areas located between the conductors.

266. The process of claim 260, further comprising etching a portion of the charge-storage layer at the isolation layers between the active strips.

267. The process of claim 266, wherein, the etching further etches a portion of the tunnel dielectric layer in the charge-storage layer from a back surface of the charge-storage material.

268. In an integrated circuit, a memory structure on a semiconductor substrate comprising isolated NOR strings of non-volatile or quasi-volatile thin-film transistors arranged in stacks, wherein each NOR string is individually accessed from circuitry in the semiconductor substrate to temporarily charge the NOR string'"'"'s intrinsic capacitance to a predetermined voltage used for programming, programming-inhibiting, erasing or reading of individual thin-film transistors in the NOR string.

269. The memory structure of claim 268, wherein the NOR strings are arranged one on top of the other in each stack, each NOR string extending along a first direction that is substantially parallel to the semiconductor substrate with spaced apart word line conductors extending along a second direction that is substantially perpendicular to the semiconductor substrate, and wherein currents in the thin-film transistor flow along a direction substantially parallel to the second direction.

270. The memory structure of claim 268, wherein the NOR strings each extend along a first direction that is substantially perpendicular to the semiconductor substrate with spaced apart word line conductors provided one on top of another and extending along a second direction that is substantially parallel to the semiconductor substrate, and wherein currents in the thin-film transistor flow along a direction substantially parallel to the second direction.

271. The memory structure of claim 268, wherein selected ones of the NOR are addressed and charged individually and programmed, program-inhibited, erased or read together in groups of one or more NOR strings.

272. The memory structure of claim 268, wherein each NOR string includes one or more thin-film transistors used to charge the NOR string'"'"'s intrinsic capacitance.

273. The memory structure of claim 268, wherein the thin-film transistors in each NOR string share a source sublayer and a drain sublayer, each thin-film transistor further comprising a channel sublayer, a word line conductor and charge trapping material in between a word line conductor and a channel sublayer.

274. emory structure of claim 273, wherein the channel sublayer of each NOR string is electrically connected to the circuitry in the substrate.

275. The memory structure of claim 273, wherein a sacrificial sublayer is provided between the shared source and drain sublayers of each NOR string prior to formation of the channel sublayer.

276. The memory structure of claim 275, wherein the sacrificial sublayer is selectively etched in part or in whole to form cavities between the second and third sublayers,

277. The memory structure of claim 276, wherein the channel sublayers of all thin-film transistors in the NOR strings of each stack are formed simultaneously.

278. The memory structure of claim 277, wherein the channel sublayers comprise one of amorphous silicon, recrystallized silicon, polycrystalline silicon, or silicon-germanium.

279. The memory structure of claim 273, wherein the channel sublayers for the thin-film transistors in each stack are formed simultaneously after the charge-trapping material is provided.

280. The memory structure of claim 273, wherein each thin-film transistor is programmed to store more than one bit of information.