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CAPACITIVE-COUPLED NON-VOLATILE THIN-FILM TRANSISTOR STRINGS IN THREE DIMENSIONAL ARRAYS

  • US 20170092371A1
  • Filed: 08/26/2016
  • Published: 03/30/2017
  • Est. Priority Date: 09/30/2015
  • Status: Active Grant
First Claim
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1. A memory circuit, comprising:

  • a semiconductor substrate having a substantially planar surface and including circuitry formed at the surface; and

    a memory array formed above the semiconductor substrate comprising a plurality of thin-film storage transistors arrayed along substantially mutually perpendicular first, second and third directions, the memory array being formed out of a semiconductor structure comprising a plurality of active strips (i) separated from each other along the first direction by a space of a predetermined distance, (ii) isolated from each other, along the second direction by a first dielectric material, and (iii) extending lengthwise along the third direction, wherein (a) each active strip comprises a first semiconductor sublayer of a first conductivity type provided between second and third semiconductor sublayers that are each of a second conductivity type, the first, second and third semiconductor sublayers providing, respectively, channel, source and drain regions of the thin-film storage transistors, (b) the thin-film storage transistors of each active strip sharing common source regions, and (c) the shared source region is electrically floating relative to the circuitry formed in the semiconductor substrate, except when one or more of the channel regions of the active strip is rendered conducting.

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