GROWTH OF CUBIC CRYSTALLINE PHASE STRUCTURE ON SILICON SUBSTRATES AND DEVICES COMPRISING THE CUBIC CRYSTALLINE PHASE STRUCTURE

• US 20170092485A1
• Filed: 12/09/2016
• Published: 03/30/2017
• Est. Priority Date: 05/04/2012
• Status: Active Grant

• Current Assignee: Rensselaer Polytechnic Institute, UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Original Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Inventors: Durniak, Mark, Brueck, Steven R.J., Lee, Seung-Chang, Wetzel, Christian
• Granted Patent: US 10,453,996 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02395 Arsenides
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02494 Structure
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02587 Structure
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/7806 involving the separation of the active layers from a substrate
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/04 with a quantum effect structure or superlattice, e.g. tunnel junction
• CPC Class Codes: H01L 33/18 within the light emitting region
• CPC Class Codes: H01L 33/32 containing nitrogen

Abstract

A method of forming a semiconductor structure includes providing a substrate comprising a first material portion and a single crystal silicon layer on the first material portion. The substrate further comprises a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface. A buffer layer is deposited in one or more of the plurality of grooves. A semiconductor material is epitaxially grown over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase.

Claims

1. A method of forming a semiconductor structure, the method comprising:

providing a substrate comprising a first material portion and a single crystal silicon layer on the first material portion, the substrate further comprising a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface;

depositing a buffer layer in one or more of the plurality of grooves;

epitaxially growing a semiconductor material over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase.

2. The method of claim 1, further comprising depositing an insulating layer on the major front surface of the substrate, prior to depositing the buffer layer, patterning the insulating layer to expose stripes of the substrate, and forming the plurality of grooves in the exposed substrate regions.

3. The method of claim 1, wherein one or more of the plurality of grooves are truncated v-grooves, each truncated v-groove comprising a first diagonal sidewall, a second diagonal sidewall opposing the first diagonal sidewall, and a bottom portion that is parallel with the major front surface of the substrate.

4. The method of claim 3, wherein the substrate is a silicon-on-insulator substrate comprising the single crystal silicon layer over a buried insulator layer, the bottom portion of the truncated v-grooves comprising a portion of the silicon layer.

5. The method of claim 3, wherein the substrate is a silicon-on-insulator substrate comprising the single crystal silicon layer over a buried insulator layer, the bottom portion of the truncated v-groove exposing a surface of the buried insulator layer.

6. The method of claim 3, wherein during the epitaxially growing of the semiconductor material a gap is formed between the hexagonal crystalline phase layers and the bottom portion of the truncated v-groove.

7. The method of claim 6, wherein at least a portion of the gap is filled with a gas.

8. The method of claim 6, wherein at least a portion of the gap is filled with a buffer layer material.

9. The method of claim 1, further comprising bonding the epitaxially grown semiconductor material to a second substrate.

10. The method of claim 9, further comprising removing at least a portion of the substrate and optionally the hexagonal crystalline phase layer.

11. The method of claim 10, wherein removing at least a portion of the substrate comprises removing the single crystal silicon layer.

12. The method of claim 10, further comprising forming a first electrode layer and a second electrode layer, both the first and second electrode layers providing for electrical contact with a semiconductor device comprising the cubic crystalline phase structure.

13. The method of claim 12, wherein the hexagonal crystalline material is removed, and further wherein the cubic crystalline phase structure has a length dimension, a width dimension and a height dimension, the width dimension decreasing with the height so that the structure is tapered, gaps being formed adjacent to the tapered structure, the method further comprising depositing a filler material in the gaps.

14. The method of claim 13, wherein epitaxially growing the semiconductor material further comprising forming at least one quantum well in the cubic crystal material, the semiconductor device being a light emitting diode.

15. The method of claim 12, wherein the hexagonal crystalline material is not removed, and further wherein the cubic crystalline phase structure has a length dimension, a width dimension and a height dimension, the width dimension decreasing with the height so that the structure is tapered, the hexagonal crystalline material being formed adjacent to the tapered structure.

16. The method of claim 1, further comprising epitaxially growing a cubic crystal material from the cubic crystalline phase structure to form a continuous cubic crystal layer.

17. A light emitting diode comprising:

a substrate comprising a Group III/V compound semiconductor material having a cubic crystalline phase, an active region being positioned in the cubic crystalline phase;

a first metal contact and a second metal contact, the first and second metal contacts being positioned to provide electrical connectivity to the light emitting diode, at least one of the first and second metal contacts being transparent to visible light;

wherein the light emitting diode is not attached to a substrate comprising a Group IV semiconductor material.

18. The light emitting diode of claim 17, wherein the cubic crystalline phase structure has a length dimension, a width dimension and a height dimension, the width dimension decreasing with the height so that the structure is tapered, the hexagonal crystalline material being formed adjacent to the tapered structure.

19. The light emitting diode of claim 18, wherein the cubic crystalline phase is positioned between a first hexagonal crystalline phase and a second hexagonal crystalline phase.

20. The light emitting diode of claim 18, wherein the Group III/V compound semiconductor material is a Group III-nitride.

21. The light emitting diode of claim 18, wherein the active region comprises one or more quantum wells.

22. An intermediate semiconductor structure comprising:

a substrate comprising a first material portion and a single crystal silicon layer positioned on the first material portion, the substrate further comprising a major front surface, a major backside surface opposing the major front surface, and a groove positioned in the major front surface;

a buffer layer disposed in the groove;

an epitaxially grown semiconductor material disposed over the buffer layer and in the groove, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase layer.

23. The semiconductor structure of claim 22, wherein the groove is a v-groove.

24. The semiconductor structure of claim 22, wherein the groove is a truncated v-groove comprising a first diagonal sidewall, a second diagonal sidewall opposing the first diagonal sidewall, and a bottom portion that is parallel with the major front surface of the substrate surface.

25. The semiconductor structure of claim 24, further comprising an insulating layer formed on the major front surface of the substrate.

26. The semiconductor structure of claim 24, further comprising a gap between the hexagonal crystalline phase layers and the bottom portion of the v-groove.

27. The semiconductor structure of claim 26, wherein at least a portion of the gap is filled with a gas.

28. The semiconductor structure of claim 26, wherein at least a portion of the gap is filled with a buffer layer material.