SELECTIVE SILICON DIOXIDE DEPOSITION USING PHOSPHONIC ACID SELF ASSEMBLED MONOLAYERS AS NUCLEATION INHIBITOR

• US 20170092533A1
• Filed: 12/02/2015
• Published: 03/30/2017
• Est. Priority Date: 09/29/2015
• Status: Abandoned Application

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Howlader, Rana, Venkatasubramanian, Eswaranand, Jan Visser, Robert, Chakraborty, Tapash, Saly, Mark, Goradia, Prerna Sonthalia, Thompson, David
• Application Number:
  US14/957,380
• Publication Number:
  US 20170092533A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02167 the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0226 formation by a deposition process per se C23C
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02307 treatment by exposure to a liquid
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 21/321 After treatment
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material

Abstract

Methods of selectively depositing a patterned layer on exposed dielectric material but not on exposed metal surfaces are described. A self-assembled monolayer (SAM) is deposited using phosphonic acids. Molecules of the self-assembled monolayer include a head moiety and a tail moiety, the head moiety forming a bond with the exposed metal portion and the tail moiety extending away from the patterned substrate and reducing the deposition rate of the patterned layer above the exposed metal portion relative to the deposition rate of the patterned layer above the exposed dielectric portion. A dielectric layer is subsequently deposited by atomic layer deposition (ALD) which cannot initiate in regions covered with the SAM in embodiments.

Claims

1. A method of forming a patterned layer on a patterned substrate, the method comprising:

selectively forming a patterned layer on the patterned substrate, wherein a deposition rate of the patterned layer on an exposed dielectric portion of the patterned substrate is at least one hundred times greater than a deposition rate of the patterned layer on an exposed metal portion of the patterned substrate, wherein the patterned layer is patterned after formation and without application of photolithography.

2. The method of claim 1 wherein the patterned layer is patterned after formation without applying any intervening photolithography or etching operations.

3. The method of claim 1 wherein the patterned layer is formed by repeated and alternating exposure to a first precursor and a second precursor.

4. The method of claim 1 wherein the patterned layer is formed by a surface chemical reaction mechanism.

5. A method of forming a patterned layer on a patterned substrate, the method comprising:

providing a patterned substrate having an exposed dielectric portion and an exposed metal portion, wherein the exposed metal portion is electrically conducting;

exposing the patterned substrate to phosphonic acid;

forming a self-assembled monolayer on the exposed metal portion but not on the exposed dielectric portion;

placing the patterned substrate in a substrate processing region;

forming the patterned layer by;

(1) flowing a first precursor into the substrate processing region,

(2) removing unused portions of the first precursor from the substrate processing region

(3) flowing a second precursor into the substrate processing region, and

(4) removing unused portions of the second precursor from the substrate processing region; and

repeating (1)-(4) an integral number of times to form a thickness of patterned layer.

6. The method of claim 5 wherein the substrate processing region is plasma-free during operations (1)-(4).

7. The method of claim 5 wherein a head moiety of a molecule of the phosphonic acid includes a PO₃H group.

8. The method of claim 5 wherein a tail moiety of a molecule of the phosphonic acid includes a perfluorinated alkyl group having more than 5 carbon atoms covalently bonded in a chain.

9. The method of claim 5 wherein a tail moiety of a molecule of the phosphonic acid includes an aromatic ring.

10. The method of claim 5 wherein a tail moiety of a molecule of the phosphonic acid includes an alkyl group having more than 12 carbon atoms covalently bonded in a chain.

11. The method of claim 5 wherein a thickness of the patterned layer exceeds 10 nm.

12. The method of claim 5 further comprising removing the self-assembled monolayer after forming the thickness of patterned layer to reexpose the exposed metal portion.

13. A method of forming a patterned layer on a patterned substrate, the method comprising:

forming a patterned dielectric layer on the patterned substrate, wherein the patterned dielectric layer has a gap;

forming an electrically conducting layer in the gap of the patterned dielectric layer;

chemical mechanical polishing the electrically conducting layer to remove metal disposed above the gap resulting in an exposed dielectric portion and an exposed metal portion;

exposing the patterned substrate to phosphonic acid;

forming a self-assembled monolayer on the exposed metal portion but not on the exposed dielectric portion;

placing the patterned substrate in a substrate processing region; and

forming the patterned layer by repeated alternating exposure to a first precursor and a second precursor, wherein a deposition rate of the patterned layer above the exposed dielectric portion is at least one hundred times greater than a deposition rate of the patterned layer above the exposed metal portion, and wherein the substrate processing region is plasma-free during the repeated alternating exposure.

14. The method of claim 13 wherein the patterned dielectric layer comprises one of SiO, SiN, SiCN.

15. The method of claim 13 wherein the exposed metal portion comprises at least one of copper, nickel, cobalt, hafnium, tantalum and tungsten.

16. The method of claim 13 wherein the exposed metal portion consists of a transition metal or a combination of transition metals.

17. The method of claim 13 wherein the exposed metal portion consists of one or more of copper, nickel, cobalt, hafnium, tantalum and tungsten.

18. The method of claim 13 wherein each molecule of the self-assembled monolayer includes a head moiety and a tail moiety, the head moiety forming a bond with the exposed metal portion and the tail moiety extending away from the patterned substrate and reducing the deposition rate of the patterned layer above the exposed metal portion relative to the deposition rate of the patterned layer above the exposed dielectric portion.

19. The method of claim 13 wherein the patterned layer is a dielectric layer.

20. The method of claim 13 wherein the patterned layer is a metal layer.

21. The method of claim 13 wherein a temperature of the patterned substrate is less than 400°

C. during each of the operation of forming the self-assembled monolayer and forming the patterned layer.