PLASMA DICING WITH BLADE SAW PATTERNED UNDERSIDE MASK

• US 20170092540A1
• Filed: 09/30/2015
• Published: 03/30/2017
• Est. Priority Date: 09/30/2015
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Rohleder, Thomas, Buenning, Hartmut, Albermann, Guido, Moeller, Sascha, Lapke, Martin
• Granted Patent: US 9,847,258 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/67092 Apparatus for mechanical treatment or grinding or cutting, see the relevant groups in subclasses B24B or B28D
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 21/82 to produce devices, e.g. integrated circuits, each consisting of a plurality of components
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body

Abstract

Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device from a wafer substrate, the wafer substrate having a top-side surface with a plurality of active device die separated by saw lanes and an opposite under-side surface. The method comprises coating the under-side surface of the wafer substrate with a resilient coating, locating the position of the saw lanes from the underside surface, blade dicing trenches in the resilient material to expose under-side bulk material in the position of saw lanes, and plasma etching through the trenches to remove the exposed under-side bulk material.

Claims

1. A method for preparing an integrated circuit (IC) device from a wafer substrate, the wafer substrate having a top-side surface with a plurality of active device die separated by saw lanes and an opposite under-side surface, the method comprising:

coating the under-side surface of the wafer substrate with a resilient material;

locating the position of the saw lanes from the underside surface;

blade dicing trenches in the resilient material to expose under-side bulk material in the position of the saw lanes; and

plasma etching through the trenches to remove the exposed under-side bulk material, the plasma etching thereby producing an etch profile characteristic of a plasma etch process.

2. The method as recited in claim 1, further comprising,

back-grinding the under-side surface of the wafer substrate;

3. The method as recited in claim 2, wherein the plasma etching includes,

a first etching with a first etch to a depth of inter-metal dielectric (IMD) layers present in the saw lanes;

and

a second etching with a second etch through the IMD layers until the plurality of active device die are separated into individual device die.

4. The method as recited in claim 3, further comprising,

etching with a third etch, the resilient coating from the underside surfaces of the individual device die.

5. The method as recited in claim 2, wherein blade dicing trenches is done to a depth of the inter-metal dielectric (IMD) layers.

6. The method as recited in claim 1,

wherein the resilient material is transparent to infra-red light;

and

wherein locating the position of the saw lanes is performed with an alignment apparatus using infra-red light transmitting through the resilient material.

7. The method as recited in claim 1, wherein locating the position of the saw lanes is performed with an alignment apparatus using pattern recognition of the topside surface of the wafer substrate.

8. The method as recited in claim 1, wherein the resilient material is an organic polymer material.

9. The method as recited in claim 1, wherein the resilient material is an underside metallization.

10. An integrated circuit (IC) device manufactured by the method as recited in claim 1.

11. An integrated circuit (IC) device die, the IC device die comprising:

a top-side portion of the device with circuit elements, surrounded by a saw lane boundary, and having a depth of at least a thickness of inter-metal dielectric (IMD) layers;

an under-side portion of bulk material extending from the IMD layers to an underside surface of the IC device die;

wherein, the top-side portion of the device has vertical side walls with an etch profile obtained from a plasma etching process; and

wherein the under-side portion of bulk material has vertical side walls with at least a partial profile obtained from a blade dicing process.

12. The IC device die as recited in claim 11, further comprising

a resilient layer, of another thickness, attached to the under-side surface.

13. The IC device as recited in claim 12, wherein the resilient layer has vertical side walls with at least a partial profile obtained from a blade dicing process.

14. The IC device as recited in claim 13, wherein the resilient material is an organic polymer layer.

15. The IC device as recited in claim 14, where in the resilient material is a metallization.