3D SEMICONDUCTOR DEVICE AND STRUCTURE

• US 20170092541A1
• Filed: 07/02/2016
• Published: 03/30/2017
• Est. Priority Date: 10/12/2009
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian
• Granted Patent: US 9,892,972 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 24/00 Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 61/20 comprising components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/84 : arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/011 : Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A 3D semiconductor device including: a first structure including first single crystal transistors; a second structure including second single crystal transistors, the second structure overlaying the first single crystal transistors, where at least one of the second single crystal transistors is at least partially self-aligned to at least one of the first single crystal transistors; and at least one thermal conducting path from at least one of the first single crystal transistors and second single crystal transistors to an external surface of the device.

Claims

1. A 3D semiconductor device, comprising:

a first structure comprising first single crystal transistors;

a second structure comprising second single crystal transistors, said second structure overlaying said first single crystal transistors,

wherein at least one of said second single crystal transistors is at least partially self-aligned to at least one of said first single crystal transistors; and

at least one thermal conducting path from at least one of said first single crystal transistors and second single crystal transistors to an external surface of said device.

2. The 3D semiconductor device according to claim 1,

wherein said second structure thickness is less than one micron.

3. The 3D semiconductor device according to claim 1,

wherein said first structure comprises a floating body memory cell.

4. The 3D semiconductor device according to claim 1, further comprising:

a third structure comprising third single crystal transistors,

wherein a plurality of said third single crystal transistors form a logic circuit.

5. The 3D semiconductor device according to claim 1,

wherein said thermal conducting path has a thermal conductivity greater than 20 W/m-K.

6. The 3D semiconductor device according to claim 1,

wherein said device comprises an electrically modifiable resistive structure.

7. The 3D semiconductor device according to claim 1,

wherein at least one of said first single crystal transistors is directly connected to at least one of said second single crystal transistors.

8. A 3D semiconductor device, comprising:

a first structure comprising first single crystal transistors;

a second structure comprising second single crystal transistors, said second structure overlaying said first single crystal transistors,

wherein at least one of said second single crystal transistors is at least partially self-aligned to at least one of said first single crystal transistors; and

a third structure comprising third single crystal transistors, said third structure overlaying said second single crystal transistors,

wherein a plurality of said third single crystal transistors form a logic circuit.

9. The 3D semiconductor device according to claim 8,

wherein said second structure thickness is less than one micron.

10. The 3D semiconductor device according to claim 8,

wherein said first structure comprises a floating body memory cell.

11. The 3D semiconductor device according to claim 8, further comprising:

at least one thermal conducting path from at least one of said first single crystal transistors and second single crystal transistors to an external surface of said device.

12. The 3D semiconductor device according to claim 8,

wherein said logic circuit is aligned to said second single crystal transistors with less than 200 nm alignment error.

13. The 3D semiconductor device according to claim 8,

wherein said device comprises an electrically modifiable resistive structure.

14. The 3D semiconductor device according to claim 8,

wherein at least one of said first single crystal transistors is directly connected to at least one of said second single crystal transistors.

15. A 3D semiconductor device, comprising:

a first structure comprising first single crystal transistors;

a second structure comprising second single crystal transistors, said second structure overlaying said first single crystal transistors,

wherein at least one of said second single crystal transistors is at least partially self-aligned to at least one of said first single crystal transistors; and

a single crystal memory control line, said single crystal memory control line is embedded in said second structure.

16. The 3D semiconductor device according to claim 15,

wherein said second structure thickness is less than one micron.

17. The 3D semiconductor device according to claim 15,

wherein said first structure comprises a floating body memory cell.

18. The 3D semiconductor device according to claim 15, further comprising:

at least one thermal conducting path from at least one of said first single crystal transistors and second single crystal transistors to an external surface of said device.

19. The 3D semiconductor device according to claim 15,

wherein said device comprises an electrically modifiable resistive structure.

20. The 3D semiconductor device according to claim 15,

wherein at least one of said first single crystal transistors is directly connected to at least one of said second single crystal transistors.