Chip Packages and Methods of Manufacture Thereof

• US 20170092617A1
• Filed: 09/30/2015
• Published: 03/30/2017
• Est. Priority Date: 09/30/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Chih-Wei, Lin, Jing-Cheng, Lu, Szu-Wei, Shih, Ying-Ching
• Granted Patent: US 9,704,825 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/061 Disposition
• CPC Class Codes: H01L 2224/11002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13024 : the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/211 : Disposition
• CPC Class Codes: H01L 2224/215 : Material
• CPC Class Codes: H01L 2224/24137 : the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24147 : the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 : the item being metallic
• CPC Class Codes: H01L 2224/33181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/73217 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/367 : Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/25 : of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1027 : IV
• CPC Class Codes: H01L 2924/1032 : III-V
• CPC Class Codes: H01L 2924/141 : Analog devices
• CPC Class Codes: H01L 2924/1421 : RF devices
• CPC Class Codes: H01L 2924/143 : Digital devices
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

Chip packages and method of manufacturing the same are disclosed. In an embodiment, a chip package may include: a redistribution layer (RDL); a first chip including a plurality of first contact pads, the plurality of first contact pads facing the RDL; a second chip disposed between the first chip and the redistribution layer (RDL) wherein a portion of the first chip is disposed outside a lateral extent of the second chip; and a conductive via laterally separated from the second chip, the conductive via extending between the RDL and a first contact pad of the plurality of first contact pads, the first contact pad located in the portion of the first chip disposed outside the lateral extent of the second chip.

Claims

1. A chip package, comprising:

a first redistribution layer (RDL);

a first chip comprising a plurality of first contact pads on a first surface of the first chip, the plurality of first contact pads facing the first RDL;

a second RDL over and contacting the first surface of the first chip, the second RDL being coupled to the plurality of first contact pads and having a same width with the first chip;

a second chip comprising a plurality of second contact pads on a first surface of the second chip, the plurality of second contact pads facing the first RDL, the second chip being laterally adjacent to the first chip;

a third RDL over and contacting the first surface of the second chip, the third RDL being coupled to the plurality of second contact pads and having a same width with the second chip, wherein the second RDL is laterally separated from the third RDL with a molding compound disposed therebetween;

a third chip disposed between the first chip and the first RDL, the third chip interposed between the second chip and the first RDL, wherein a portion of the first chip is disposed outside a lateral extent of the third chip, wherein a portion of the second chip is disposed outside the lateral extent of the third chip, and wherein the third chip comprises a plurality of third contact pads facing the first RDL; and

a conductive via laterally separated from the third chip, the conductive via extending between the first RDL and a first contact pad of the plurality of first contact pads, the first contact pad located in the portion of the first chip disposed outside the lateral extent of the third chip, wherein an end of the conductive via adjacent to the first RDL is coplanar with pillars on the plurality of third contact pads of the third chip.

2. The chip package of claim 1, wherein the first chip and the third chip differ in function.

3. The chip package of claim 1, wherein the first chip and the third chip comprise a dynamic random access memory (DRAM) chip and a logic chip, respectively.

5. The chip package of claim 1, wherein the molding compound encapsulates the first chip, the second chip, the third chip, and the conductive via.

6. The chip package of claim 1, further comprising a first adhesive layer, wherein a first portion of the first adhesive layer is disposed between the first chip and the third chip, wherein a second portion of the first adhesive layer is disposed between the second chip and the third chip.

7. The chip package of claim 1, further comprising a polymer layer disposed between the third chip and the first RDL.

8. The chip package of claim 7, wherein the polymer layer comprises at least one of polyimide (PI), polybenzoxazole (PBO), benzocyclobuten (BCB), epoxy, silicone, acrylates, nano-filled pheno resin, siloxane, a fluorinated polymer, or polynorbornene.

12. The chip package of claim 2, wherein the molding compound and the adhesive layer differ in composition.

4. (canceled)

9. A chip package, comprising:

a plurality of dynamic random access memory (DRAM) chips laterally adjacent to each other, each of the plurality of DRAM chips having a plurality of first contact pads on a first surface thereof;

a logic chip attached to the first surfaces of the plurality of DRAM chips, the logic chip having a plurality of second contact pads on a first surface thereof, wherein the first surface of the logic chip faces away from the plurality of DRAM chips, wherein the plurality of DRAM chips extend beyond lateral extents of the logic chip;

an adhesive layer between the logic chip and the plurality of DRAM chips, the adhesive layer contacting a second surface of the logic chip opposing the first surface of the logic chip, the adhesive layer having a same width as the logic chip, a first portion of the adhesive layer being attached to a first one of the plurality of DRAM chips, and a second portion of the adhesive layer being attached to a second one of the plurality of DRAM chips;

a plurality of first conductive pillars having first ends coupled to the plurality of second contact pads of the logic chip;

a first redistribution layer (RDL) coupled to second ends of the plurality of first conductive pillars opposite the first ends;

a plurality of second conductive pillars laterally separated from the logic chip, the plurality of second conductive pillars extending from the first RDL to corresponding ones of a first group of the plurality of first contact pads, the first group disposed outside a width of the logic chip; and

a molding compound around the plurality of DRAM chips, the logic chip, the adhesive layer, and the plurality of second conductive pillars.

10. The chip package of claim 9, further comprising a polymer layer disposed within the width of the logic chip and encapsulating the plurality of first conductive pillars.

13. The chip package of claim 9, further comprising a heat sink attached to second surfaces of the plurality of DRAM chips opposing respective first surfaces of the plurality of DRAM chips.

14. The chip package of claim 9, further comprising a plurality of external connectors disposed at a surface of the first RDL facing away from the logic chip.

21. The chip package of claim 9, wherein the plurality of second conductive pillars contact the first group of the plurality of first contact pads.

22. The chip package of claim 9, further comprising a second RDL between the plurality of DRAM chips and the adhesive layer, wherein the second RDL extends beyond the lateral extents of the logic chip, wherein a first portion of the second RDL is coupled to a first one of the plurality of DRAM chips, and a second portion of the second RDL is coupled to a second one of the plurality of DRAM chips.

23. The chip package of claim 22, wherein the first portion of the second RDL is spaced apart from the second portion of the second RDL, wherein the molding compound fills a gap between the first portion of the second RDL and the second portion of the second RDL.

24. The chip package of claim 22, wherein a third portion of the second RDL is disposed between and connects the first portion of the second RDL and the second portion of the second RDL.

11. (canceled)

15. (canceled)

16. A method, comprising:

placing a first die and a second die over a carrier, the first die and the second die being laterally adjacent to each other, the first die and the second die each having a plurality of first contact pads on an upper surface thereof, the upper surface facing away from the carrier;

forming a first conductive pillar over a peripheral contact pad of the plurality of first contact pads of the first die;

attaching a third die to the upper surface of the first die and to the upper surface of the second die after the placing, the first die and the second die extending beyond a lateral extent of the third die, a first portion of the third die being attached to the first die, a second portion of the third die being attached to the second die, the third die being laterally adjacent to the first conductive pillar, the third die having a plurality of second contact pads facing away from the carrier and a plurality of second conductive pillars, each of the plurality of second conductive pillars being on a corresponding one of the plurality of second contact pads;

embedding the first die, the second die, the third die and the first conductive pillar in a molding compound after the attaching;

removing a portion of the molding compound after the embedding until a top surface of the plurality of second conductive pillars die and a top surface of the first conductive pillar are exposed and coplanar; and

subsequently, forming a first redistribution layer (RDL) over the molding compound, the first RDL electrically coupled to the plurality of second conductive pillars and the first conductive pillar.

17. The method of claim 16, further comprising removing the carrier and attaching a heat sink to surfaces of the first die and the second die facing away from the first RDL after the forming the first RDL.

25. The method of claim 16, further comprising:

after the placing and before the forming the first conductive pillar, forming a second RDL over the plurality of first contact pads of the first die and over the plurality of first contact pads of the second die, wherein the second RDL extends continuously from the first die to the second die.

26. The method of claim 16, further comprising:

after the placing and before the forming the first conductive pillar, forming a second RDL over the first die and a third RDL over the second die, wherein the second RDL and the third RDL are spaced apart from each other.

18-20. -20. (canceled)