INTEGRATED REACTIVE MATERIAL ERASURE ELEMENT WITH PHASE CHANGE MEMORY

• US 20170092694A1
• Filed: 09/30/2015
• Published: 03/30/2017
• Est. Priority Date: 09/30/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: BrightSky, Matthew J., Cabral, Cyril Jr., Rodbell, Kenneth P.
• Granted Patent: US 10,535,713 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0059 Security or protection circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 2013/008 Write by generating heat in the surroundings of the memory material, e.g. thermowrite
• CPC Class Codes: G11C 2213/50 Resistive cell structure aspects
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8613 Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A reactive material erasure element comprising a reactive material is located between PCM cells and is in close proximity to the PCM cells. The reaction of the reactive material is trigger by a current applied by a bottom electrode which has a small contact area with the reactive material erasure element, thereby providing a high current density in the reactive material erasure element to ignite the reaction of the reactive material. Due to the close proximity of the PCM cells and the reactive material erasure element, the heat generated from the reaction of the reactive material can be effectively directed to the PCM cells to cause phase transformation of phase change material elements in the PCM cells, which in turn erases data stored in the PCM cells.

Claims

1. A semiconductor structure comprising:

a phase change memory (PCM) cell comprising a first bottom electrode, a phase change material element and a top electrode; and

a reactive material (RM) erasure element located on one side of the PCM cell and contacting a top surface of a second bottom electrode.

2. The semiconductor structure of claim 1, wherein a lateral distance between the PCM cell and the RM erasure element is from 0.5 μ

m to 5 μ

m.

3. The semiconductor structure of claim 1, wherein the phase change material element comprises Ge₂Sb₂Te₅ (GST), SbTe or In₂Se₃, and wherein the RM erasure element comprises Al/Pd, Ni/Al, Cu/Pd, Si/Cr or SiO₂/Al.

4. The semiconductor structure of claim 1, wherein an area of a top contact surface of each of the first and the second bottom electrodes ranges from 10 nm² to 1000 nm².

5. The semiconductor structure of claim 1, wherein the first and the second bottom electrodes are laterally surrounded by an insulator layer and contact top surfaces of bottom contact structures that are electrically coupled to an access circuitry.

6. The semiconductor structure of claim 5, wherein a stack of the phase change material element and the top electrode and the RM erasure element are laterally surrounded by a first dielectric layer that is present over the insulator layer and the first and the second bottom electrodes, wherein a top surface of the first dielectric layer is located above top surfaces of the top electrode and the RM erasure element.

7. The semiconductor structure of claim 6, further comprising a dielectric fill portion located over the RM erasure element.

8. The semiconductor structure of claim 7, further comprising a first contact via structure contacting a top surface of the top electrode, and a second contact via structure contacting a top surface of one of the bottom contact structures that is electrically coupled to a periphery circuitry.

9. The semiconductor structure of claim 8, further comprising a first interconnect structure contacting a top surface of the first contact via structure, and a second interconnect structure contacting a top surface of the second via structure, wherein the first interconnect structure and the second interconnect structure are laterally surrounded by a second contact level dielectric layer.

10. A semiconductor structure comprising:

an array of phase change memory (PCM) cells arranged in rows and columns, wherein each of the PCM cells comprises a first bottom electrode, a phase change material element and a top electrode; and

at least one reactive material (RM) erasure element, wherein the at least one RM erasure elements is disposed between each pair of adjacent columns of the PCM cells and contacts a top surface of a second bottom electrode.

11. The semiconductor structure of claim 10, wherein a lateral distance between the at least one RM erasure element and an adjacent PCM cell is from 0.5 μ

m to 5 μ

m.

12. The semiconductor structure of claim 10, further comprising a pair of electrical contacts providing electrical communication between a voltage source and the at least one RM erasure element.

13. The semiconductor structure of claim 12, wherein the pair of electrical contacts is located at opposite ends of the at least one RM erasure element.

14. The semiconductor structure of claim 12, wherein the at least one RM erasure element is a contiguous layer, and the pair of electrical contacts is located at one end of the at least one RM erasure element.

15. A method for forming a semiconductor structure comprising:

forming a first bottom electrode and a second bottom electrode extending through an insulator layer, wherein the first bottom electrode contacts a top surface of a first bottom contact structure and the second bottom electrode contacts a top surface of a second bottom contact structure, the first and second bottom contact structures electrically coupled to an access circuitry;

forming a stack of, from bottom to top, a phase change material element and a top electrode contacting a top surface of the first bottom electrode;

forming a dielectric layer over the stack, the second bottom electrode and the insulator layer;

forming a trench extending through the dielectric layer, the trench exposing the second bottom electrode;

forming a reactive material (RM) erasure element in the trench, wherein the RM erasure element has a top surface located below a top surface of the dielectric layer; and

forming a trench fill portion over the RM erasure element to completely fill the trench.

16. The method of claim 15, wherein a lateral distance between a sidewall of the trench and a proximal sidewall of the stack is from 0.5 μ

m to 5 μ

m.

17. The method of claim 15, wherein an area of a top contact surface of each of the first and the second bottom electrodes ranges from 10 nm² to 1000 nm².

18. The method of claim 15, wherein the forming the trench comprises:

forming a mask layer over the dielectric layer, wherein the mask layer comprises a release layer and a photoresist layer overlying the release layer;

forming an opening in the mask layer at a location adjacent to the stack by lithography patterning and etching, wherein an undercut is formed in the release layer during the lithography patterning and etching; and

removing a portion of the dielectric layer exposed by the opening.

19. The method of claim 15, further comprising forming a first dielectric cap layer over the first and the second bottom electrodes, wherein the trench extends through the first dielectric cap layer.

20. The method of claim 15, wherein the forming the dielectric fill portion comprises:

forming a second dielectric cap layer over the first contact level and the RM erasure element;

depositing a dielectric material over the second dielectric cap layer; and

removing the deposited dielectric material from a top surface of the second dielectric cap layer.