ERROR LOCATOR POLYNOMIAL DECODER AND METHOD
First Claim
Patent Images
1. An apparatus comprising:
- an error locator polynomial generator circuit; and
a convergence detector circuit coupled to the error locator polynomial generator circuit, the convergence detector circuit including;
at least two computation circuits configured to generate at least two convergence signals based on a mutual error locator polynomial from the error locator polynomial generator circuit and on at least two different sets of syndromes, wherein each of the different sets of syndromes corresponds to a different one of the convergence signals.
4 Assignments
0 Petitions
Accused Products
Abstract
An apparatus includes a convergence detector circuit coupled to an error locator polynomial generator circuit. The convergence detector circuit includes at least two computation circuits configured to generate at least two convergence signals based on a mutual error locator polynomial from the error locator polynomial generator circuit and on at least two different sets of syndromes. Each of the different sets of syndromes corresponds to a different one of the convergence signals.
11 Citations
20 Claims
-
1. An apparatus comprising:
-
an error locator polynomial generator circuit; and a convergence detector circuit coupled to the error locator polynomial generator circuit, the convergence detector circuit including; at least two computation circuits configured to generate at least two convergence signals based on a mutual error locator polynomial from the error locator polynomial generator circuit and on at least two different sets of syndromes, wherein each of the different sets of syndromes corresponds to a different one of the convergence signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A method comprising:
-
initiating an iterative error locator polynomial generation operation that is scheduled for a particular number of iterations; during an iteration prior to a final scheduled iteration of the error locator polynomial generation operation, concurrently testing multiple iterations of convergence criteria to determine if a later iteration of the error locator polynomial generation operation is configured to change an error locator polynomial; and terminating the error locator polynomial generation operation prior to the final scheduled iteration in response to determining that no later iteration of the error locator polynomial is configured to change the error locator polynomial. - View Dependent Claims (13)
-
-
14. An apparatus comprising:
-
means for generating an error locator polynomial; means for generating a first convergence signal based on the error locator polynomial and corresponding to a first set of syndromes; and means for generating, concurrently with generation of the first convergence signal, a second convergence signal based on the error locator polynomial and corresponding to a second set of syndromes. - View Dependent Claims (15, 16)
-
-
17. An apparatus comprising:
-
an error locator polynomial generator circuit configured to adjust an error locator polynomial based on an error parity; a root solver circuit coupled to an output of the error locator polynomial generator circuit; and a direct solver circuit in parallel with operation of the error locator polynomial generator circuit and configured to determine at least one error location. - View Dependent Claims (18, 19, 20)
-
Specification