CIRCUIT, A TIME-TO-DIGITAL CONVERTER, AN INTEGRATED CIRCUIT, A TRANSMITTER, A RECEIVER AND A TRANSCEIVER

• US 20170097613A1
• Filed: 12/15/2016
• Published: 04/06/2017
• Est. Priority Date: 06/23/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel IP Corporation (Intel Corporation)
• Inventors: Tertinek, Stefan, Leistner, Andreas
• Granted Patent: US 9,851,696 B2
• Time in Patent Office: Days
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H03M 1/08 of noise H03M1/0617 takes precedence

Abstract

A circuit according to an example includes a controllable oscillator configured to generate an output signal based on a control signal, an input signal processing circuit configured to receive a reference signal and configured to generate a sequence of digital values indicative of a phase relation between the reference signal and the output signal or a signal derived from the output signal, and a digital data processing circuit configured to generate a sequence of processed values at a lower frequency than a frequency of the sequence of the digital values, each processed value being based on a plurality of the digital values of the sequence of digital values, wherein the control signal is based on the sequence of processed values.

Claims

1. A circuit comprising:

a controllable oscillator configured to generate an output signal based on a control signal;

an input signal processing circuit configured to receive a reference signal and generate a sequence of digital values indicating a phase relation between the reference signal and the output signal or a signal derived from the output signal;

a digital data processing circuit configured to generate a sequence of processed values at a lower frequency than a frequency of the sequence of the digital values, wherein each processed value is based on a plurality of the digital values of the sequence of digital values,

wherein the control signal is based on the sequence of processed values; and

a noise cancellation circuit coupled between the input signal processing circuit and the controllable oscillator and configured to compensate a phase shift caused by a switching of a frequency divider coupled between the controllable oscillator and the input processing circuit,

wherein the noise cancellation circuit outputs a value indicative of the phase shift.

2. The circuit according to claim 1, wherein the digital data processing circuit is configured to generate the sequence of processed values by digitally processing the plurality of the digital values.

3. The circuit according to claim 1, further comprising a loop filter coupled between the digital data processing circuit and the controllable oscillator and configured to generate the control signal based on the processed values.

4. The circuit according to claim 1, wherein the frequency divider coupled between the controllable oscillator and the input signal processing circuit is configured to provide the input signal processing circuit with a feedback signal as the signal derived from the output signal, the feedback signal being a frequency divided output signal.

5. The circuit according to claim 4, wherein the frequency divider is a multi-modulus divider configured to divide the frequency of the output signal by one of at least two different dividers to provide the feedback signal in response to a divider control signal.

6. The circuit according to claim 5, further comprising a divider control circuit configured to generate the divider control signal based on a control value.

7. The circuit according to claim 6, wherein the divider control circuit is configured to generate the divider control signal such that the multi-modulus divider switches between at least two different dividers.

8. The circuit according to claim 5, wherein the divider control circuit operates at a higher operating frequency than the frequency of the sequence of processed values.

9. The circuit according to claim 8, wherein the divider control circuit operates at the same operation frequency as the frequency of the sequence of digital values.

10. The circuit according to claim 5, wherein the divider control circuit comprises a sigma-delta-modulator configured to generate the divider control signal.

11. The circuit according to claim 10, wherein the divider control circuit further comprises a divider to divide the control value according to the ratio of the frequency of the sequence of the digital values with respect to the frequency of sequence of processed values.

12. The circuit according to claim 1, further comprising a further digital data processing circuit to generate a sequence of values indicative of an over-all phase shift.

13. The circuit according to claim 12, wherein the further digital data processing circuit is configured to generate the sequence of values indicative of the over-all phase shift using the same system function as the digital data processing circuit, wherein the system function is indicative of processing the plurality of digital values to obtain a processed value.

14. The circuit according to claim 12, wherein the noise cancellation circuit further comprises a multiplier configured to generate a cancellation signal based on the values indicative of the over-all phase shift, wherein the noise cancellation circuit is configured to combine the cancellation signal with the signal received by the noise cancellation circuit.

15. The circuit according to claim 1, wherein the noise cancellation circuit is directly coupled to an output of the digital data processing circuit.

16. The circuit according to claim 1, wherein the noise cancellation circuit is directly coupled to an input of the digital data processing circuit.

17. The circuit according to claim 1, further comprising a reference signal generator configured to generate the reference signal.

18. The circuit according to claim 17, wherein the reference signal generator comprises a reference clock signal generator configured to generate a reference clock signal and a frequency multiplier circuit, the frequency multiplier circuit being configured to generate the reference signal as a frequency multiplied signal based on the reference clock signal.

19. A time-to-digital converter comprising:

an input signal processing circuit configured to receive at least one input signal and configured to generate a sequence of digital values indicative of time intervals concerning events comprised in the at least one input signal;

a digital data processing circuit configured to generate a sequence of processed values at a lower frequency than a frequency of the sequence of the digital values, wherein each processed value is based on a plurality of the digital values of the sequence of digital values; and

a noise cancellation circuit coupled to an output of the digital data processing circuit, and configured to compensate a phase shift,

wherein the noise cancellation circuit outputs a value indicative of the phase shift.

20. An integrated circuit comprising a circuit, the circuit comprising:

a controllable oscillator configured to generate an output signal based on a control signal;

an input signal processing circuit configured to receive a reference signal and to generate a sequence of digital values indicating a phase relation between the reference signal and the output signal or a signal derived from the output signal;

a digital data processing circuit configured to generate a sequence of processed values at a lower frequency than a frequency of the sequence of the digital values, wherein each processed value is based on a plurality of the digital values of the sequence of digital values,

wherein the control signal is based on the sequence of processed values; and

a noise cancellation circuit coupled between the input signal processing circuit and the controllable oscillator and configured to compensate a phase shift caused by a switching of a frequency divider coupled between the controllable oscillator and the input signal processing circuit,

wherein the noise cancellation circuit outputs a value indicative of the phase shift.