PIPELINED CONVOLUTIONAL OPERATIONS FOR PROCESSING CLUSTERS
First Claim
1. One or more integrated circuits (ICs) comprising:
- controller circuitry to;
receive a command to execute an operation for a plurality of data inputs stored in an external memory or a local memory; and
convert the operation into a set of matrix operations to operate on sub-portions of the plurality of data inputs; and
at least one processing circuitry to execute the set of matrix operations, the processing circuitry to include;
arithmetic logic units (ALUs);
a local memory external to the ALUs and accessible by the ALUs; and
processing control circuitry to;
create at least one matrix operand in the local memory from the plurality of data inputs of the operation, the at least one matrix operand comprising at least one of a scalar, a vector, or a two-dimensional (2D) matrix; and
provide memory handles corresponding to each of the matrix operands to one of the ALUs to access the respective matrix operands when executing one of the matrix operations.
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Accused Products
Abstract
Described herein are one or more integrated circuits (ICs) comprising controller circuitry to receive a command to execute an operation for data inputs stored in an external memory or a local memory, and convert the operation into a set of matrix operations to operate on sub-portions of the data inputs. The IC(s) further comprise at least one processing circuitry to execute the set of matrix operations, the processing circuitry to include ALUs, a local memory external to the ALUs and accessible by the ALUs, and processing control circuitry to create at least one matrix operand in the local memory (from the data inputs of the operation) comprising at least one of a scalar, a vector, or a 2D matrix, and provide memory handles corresponding to each of the matrix operands to one of the ALUs to access the respective matrix operands when executing a matrix operation.
35 Citations
20 Claims
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1. One or more integrated circuits (ICs) comprising:
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controller circuitry to; receive a command to execute an operation for a plurality of data inputs stored in an external memory or a local memory; and convert the operation into a set of matrix operations to operate on sub-portions of the plurality of data inputs; and at least one processing circuitry to execute the set of matrix operations, the processing circuitry to include; arithmetic logic units (ALUs); a local memory external to the ALUs and accessible by the ALUs; and processing control circuitry to; create at least one matrix operand in the local memory from the plurality of data inputs of the operation, the at least one matrix operand comprising at least one of a scalar, a vector, or a two-dimensional (2D) matrix; and provide memory handles corresponding to each of the matrix operands to one of the ALUs to access the respective matrix operands when executing one of the matrix operations. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A system comprising:
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a host processor; a host memory; an input/output (I/O) interface; a memory separate from the host memory; and one or more integrated circuits (ICs) comprising; controller circuitry to; receive a command to execute an operation for a plurality of data inputs stored in an external memory or a local memory; and convert the operation into a set of matrix operations to operate on sub-portions of the plurality of data inputs; and at least one processing circuitry to execute the set of matrix operations, the processing circuitry to include; arithmetic logic units (ALUs); a local memory external to the ALUs and accessible by the ALUs; and processing control circuitry to; create at least one matrix operand in the local memory from the plurality of data inputs of the operation, the at least one matrix operand comprising at least one of a scalar, a vector, or a two-dimensional (2D) matrix; and provide memory handles corresponding to each of the matrix operands to one of the ALUs to access the respective matrix operands when executing one of the matrix operations. - View Dependent Claims (18, 19, 20)
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Specification