FABRICATION OF SHIELDED GATE TRENCH MOSFET WITH INCREASED SOURCE-METAL CONTACT

• US 20170098695A1
• Filed: 12/19/2016
• Published: 04/06/2017
• Est. Priority Date: 08/14/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Chen, John
• Granted Patent: US 10,411,104 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Forming a semiconductor device on a semiconductor substrate having a substrate top surface includes: forming a gate trench extending from the substrate top surface into the semiconductor substrate; forming a gate electrode in the gate trench; forming a curved sidewall portion along at least a portion of a sidewall of the gate trench; forming a body region adjacent to the gate trench; forming a source region embedded in the body region, including disposing source material in a region that is along at least a part of the curved sidewall portion; forming a gate top dielectric layer over the gate electrode and having a top side that is below at least a portion of the source region; and forming a metal layer over at least a portion of a gate trench opening and at least a portion of the source region.

Claims

1. A method of forming a semiconductor device on a semiconductor substrate having a substrate top surface, comprising:

forming a gate trench extending from the substrate top surface into the semiconductor substrate;

forming a gate electrode in the gate trench;

forming a curved sidewall portion along at least a portion of a sidewall of the gate trench;

forming a body region adjacent to the gate trench;

forming a source region embedded in the body region, including disposing source material in a region that is along at least a part of the curved sidewall portion;

forming a gate top dielectric layer over the gate electrode and having a top side that is below at least a portion of the source region; and

forming a metal layer over at least a portion of a gate trench opening and at least a portion of the source region.

2. The method of claim 1, wherein the forming of the metal layer includes forming the metal layer to cover the gate top dielectric layer and to contact at least a portion of a sidewall of the source region facing the gate top dielectric layer.

3. The method of claim 1, further comprising:

disposing an inter-electrode dielectric material; and

forming a shield electrode within the gate trench that is separated from the gate electrode by the inter-electrode dielectric material.

4. The method of claim 1, wherein the forming of the metal layer includes making at least a portion of the metal layer to be in contact with at least a portion of the source region.

5. The method of claim 1, further comprising forming a contact trench;

and wherein

the forming of the metal layer includes forming the metal layer to be in contact with the source region at;

at least a portion of a side of the source region facing the contact trench, and at least a portion of the source region facing the gate top dielectric layer.

6. The method of claim 1, wherein the forming of the gate top dielectric layer includes:

disposing a gate top dielectric material over the gate electrode; and

removing a portion of the gate top dielectric material to cause a top side of the gate top dielectric layer to be below a top side of the source region.

7. The method of claim 1, wherein the forming of the curved sidewall portion includes forming a convex curvature with respect to the source region.

8. The method of claim 1, wherein the forming of the metal layer includes forming the metal layer to be in contact with the source region on multiple sides.

9. The method of claim 1, further comprising forming a contact trench.

10. The method of claim 1, further comprising:

forming a contact trench; and

forming a conductive plug within the contact trench.

11. The method of claim 1, wherein the forming of the gate trench includes forming the gate trench to include a portion that is substantially vertical with respect to the substrate top surface.

12. A method of forming a semiconductor device on a semiconductor substrate having a substrate top surface, comprising:

forming a gate trench extending from the substrate top surface into the semiconductor substrate;

forming a first electrode in the gate trench;

disposing an inter-electrode dielectric material that separates the first electrode from a second electrode in the gate trench;

forming the second electrode in the gate trench;

forming a body region adjacent to the gate trench;

forming a source region embedded in the body region;

forming a dielectric layer in the gate trench, above the first electrode and the second electrode, the forming of the dielectric layer including forming a top side of the dielectric layer such that the source region extend above a top side of the dielectric layer;

forming a contact trench that allows contact between the source region and the body region; and

forming a metal layer over at least a portion of the gate trench opening and at least a portion of the source region;

wherein;

the forming of the source region includes forming a first side that is substantially aligned with a sidewall of the gate trench, and a second side that is substantially aligned with a sidewall of the contact trench; and

the forming of the metal layer includes forming the metal layer to be in contact with the source region at;

at least a portion of the first side and at least a portion of the second side.

13. The method of claim 12, wherein:

the forming of the source region further includes forming a top side between the first side and the second side; and

the forming of the metal layer further includes forming the metal layer to be in contact with the source region at at least a portion of the top side.