PERFORMANCE OF COPROCESSOR ASSISTED MEMSET() THROUGH HETEROGENEOUS COMPUTING

• US 20170102892A1
• Filed: 10/09/2015
• Published: 04/13/2017
• Est. Priority Date: 10/09/2015
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Pusukuri, Kishore, Gardner, Robert D.
• Granted Patent: US 9,823,871 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/109 for multiple virtual address spaces, e.g. segmentation G06F12/1036 takes precedence
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system

Abstract

Techniques herein perform coprocessor assisted memory filling in a pipeline. A computer receives a request to fill multiple ranges of memory addresses with a value. The computer selects a first subset of the multiple ranges and distributes the first subset of ranges to multiple coprocessors. The coprocessors begin to fill the memory locations of the first subset of ranges with the value. At the same time as the coprocessors fill the first subset of ranges, the computer selects a second subset of the multiple ranges of memory addresses. Also while the coprocessors are still filling the first subset of ranges, the computer distributes the second subset of ranges to the coprocessors This overlapping activity achieves a processing pipeline that can be extended for any amount of additional subsets of memory ranges.

Claims

1. A method comprising:

receiving a request to fill a plurality of ranges of memory addresses with a value;

selecting a first subset of said plurality of ranges;

distributing said first subset of ranges to a plurality of coprocessors;

after said distributing said first subset, selecting a second subset of said plurality of ranges, wherein said second subset and said first subset are disjoint;

distributing said second subset of ranges to said plurality of coprocessors.

2. The method of claim 1 wherein distributing said first subset of ranges comprises distributing multiple ranges of said first subset of ranges to one of said plurality of coprocessors.

3. The method of claim 1 wherein:

said plurality of ranges of memory addresses comprises a plurality of ranges of physical memory addresses;

said plurality of physical memory addresses are associated with one range of virtual memory addresses;

said value is zero.

4. The method of claim 1 wherein:

said distributing said first subset of ranges to a plurality of coprocessors comprises for each range of said first subset of ranges, adding a command to a command queue of a respective coprocessor of said plurality of coprocessors;

said command identifies said each range and contains said value.

5. The method of claim 1 wherein distributing said first subset of ranges to a plurality of coprocessors comprises distributing at least one of said first subset of ranges to a central processing unit (CPU).

6. The method of claim 5 wherein distributing at least one of said first subset of ranges to a CPU comprises distributing more memory addresses to said CPU than are distributed to at least one of said plurality of coprocessors.

7. The method of claim 1 wherein said selecting a first subset of said plurality of ranges comprises splitting at least one of said plurality of ranges into a plurality of subranges.

8. One or more non-transitory computer readable media storing instructions that include:

first instructions which, when executed by one or more processors, cause receiving a request to fill a plurality of ranges of memory addresses with a value;

second instructions which, when executed by one or more processors, cause selecting a first subset of said plurality of ranges;

third instructions which, when executed by one or more processors, cause distributing said first subset of ranges to a plurality of coprocessors;

fourth instructions which, when executed by one or more processors, cause after said distributing said first subset, selecting a second subset of said plurality of ranges, wherein said second subset and said first subset are disjoint;

fifth instructions which, when executed by one or more processors, cause distributing said second subset of ranges to said plurality of coprocessors.

9. The one or more non-transitory computer readable media of claim 8 wherein distributing said first subset of ranges comprises distributing multiple ranges of said first subset of ranges to one of said plurality of coprocessors.

10. The one or more non-transitory computer readable media of claim 8 wherein:

said plurality of ranges of memory addresses comprises a plurality of ranges of physical memory addresses;

said plurality of physical memory addresses are associated with one range of virtual memory addresses;

said value is zero.

11. The one or more non-transitory computer readable media of claim 8 wherein:

said distributing said first subset of ranges to a plurality of coprocessors comprises for each range of said first subset of ranges, adding a command to a command queue of a respective coprocessor of said plurality of coprocessors;

said command identifies said each range and contains said value.

12. The one or more non-transitory computer readable media of claim 8 wherein distributing said first subset of ranges to a plurality of coprocessors comprises distributing at least one of said first subset of ranges to a central processing unit (CPU).

13. The one or more non-transitory computer readable media of claim 12 wherein distributing at least one of said first subset of ranges to a CPU comprises distributing more memory addresses to said CPU than are distributed to each of said plurality of coprocessors.

14. The one or more non-transitory computer readable media of claim 8 wherein said selecting a first subset of said plurality of ranges comprises splitting at least one of said plurality of ranges into a plurality of subranges.

15. A device comprising:

a plurality of coprocessors capable of storing a value at the memory addresses of a range of memory addresses; and

a central processing unit (CPU) connected to said plurality of coprocessors and configured to;

receive a request to fill a plurality of ranges of memory addresses with a value;

select a first subset of said plurality of ranges;

distribute said first subset of ranges to a plurality of coprocessors;

after said distributing said first subset, select a second subset of said plurality of ranges, wherein said second subset and said first subset are disjoint;

distribute said second subset of ranges to said plurality of coprocessors.

16. The device of claim 15 wherein distributing said first subset of ranges comprises distributing multiple ranges of said first subset of ranges to one of said plurality of coprocessors.

17. The device of claim 15 wherein:

said plurality of ranges of memory addresses comprises a plurality of ranges of physical memory addresses;

said plurality of physical memory addresses are associated with one range of virtual memory addresses;

said value is zero.

18. The device of claim 15 wherein:

said distributing said first subset of ranges to a plurality of coprocessors comprises for each range of said first subset of ranges, adding a command to a command queue of a respective coprocessor of said plurality of coprocessors;

said command identifies said each range and contains said value.

19. The device of claim 15 wherein distributing said first subset of ranges to a plurality of coprocessors comprises distributing at least one of said first subset of ranges to a central processing unit (CPU).

20. The method of claim 19 wherein distributing at least one of said first subset of ranges to a CPU comprises distributing more memory addresses to said CPU than are distributed to each of said plurality of coprocessors.

21. The device of claim 15 wherein said selecting a first subset of said plurality of ranges comprises splitting at least one of said plurality of ranges into a plurality of subranges.