NEURAL NETWORK UNIT THAT PERFORMS STOCHASTIC ROUNDING

• US 20170102920A1
• Filed: 04/05/2016
• Published: 04/13/2017
• Est. Priority Date: 10/08/2015
• Status: Active Grant

• Current Assignee: Via Alliance Semiconductor Co., Ltd.
• Original Assignee: Via Alliance Semiconductor Co., Ltd.
• Inventors: HENRY, G. GLENN, PARKS, TERRY
• Granted Patent: US 10,353,862 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 15/82 data or demand driven
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/49947 Rounding
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/321 Program or instruction counter, e.g. incrementing
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3893 controlled in tandem, e.g. multiplier-accumulator
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G06N 3/044 Recurrent networks, e.g. Hopfield networks
• CPC Class Codes: G06N 3/045 : Combinations of networks
• CPC Class Codes: G06N 3/063 : using electronic means
• CPC Class Codes: G06N 3/065 : Analogue means
• CPC Class Codes: G06N 3/08 : Learning methods
• CPC Class Codes: G06N 3/088 : Non-supervised learning, e.g. competitive learning

Abstract

A neural network unit includes a random bit source that generates random bits and a plurality of neural processing units (NPU). Each NPU includes an accumulator into which the NPU accumulates a plurality of products as an accumulated value and a rounder that receives the random bits from the random bit source and stochastically rounds the accumulated value based on a random bit received from the random bit source.

Claims

1. A neural network unit, comprising:

a random bit source that generates random bits; and

a plurality of neural processing units (NPU), each NPU comprising;

an accumulator into which the NPU accumulates a plurality of products as an accumulated value; and

a rounder that receives the random bits from the random bit source and stochastically rounds the accumulated value based on a random bit received from the random bit source.

2. The neural network unit of claim 1, further comprising:

a register programmable with a rounding mode, and the rounder stochastically rounds the accumulated value based on the random bit received from the random bit source when the rounding mode indicates stochastic round, and employs a different rounding mode when the rounding mode indicates the different rounding mode.

3. The neural network unit of claim 1, the accumulated value is a fixed-point arithmetic value.

4. The neural network unit of claim 3, further comprising:

a register programmable with a binary point location of the fixed-point arithmetic accumulated value, the binary location specifies a number of fractional bits of the fixed-point arithmetic accumulated value.

5. The neural network unit of claim 4, the rounder rounds the accumulated value in response to the NPU aligning the accumulated value to an output representation that has fewer fractional bits than the number of fractional bits programmed into the register.

6. The neural network unit of claim 5, further comprising:

a second register programmable with a binary point location of the output representation.

7. The neural network unit of claim 1, the NPU computes each of the plurality of products from first and second operands, and each of the first and second operands is a fixed-point arithmetic value.

8. The neural network unit of claim 7, further comprising:

a first register programmable with a binary point location of the first operand; and

a second register programmable with a binary point location of the second operand.

9. The neural network unit of claim 1, each of the plurality of products is a fixed-point arithmetic value.

10. The neural network unit of claim 1, the random bit source generates the random bits based on a sampling of random electrical characteristics of an integrated circuit that embodies the neural network unit.

11. A method for operating a neural network unit having a plurality of neural processing units (NPU), the method comprising:

generating, by a random bit source, random bits; and

by each NPU;

accumulating into an accumulator a plurality of products as an accumulated value;

receiving, by a rounder, the random bits from the random bit source; and

stochastically rounding, by the rounder, the accumulated value based on a random bit received from the random bit source.

12. The method of claim 11, further comprising:

programming a register with a rounding mode;

said stochastically rounding, by the rounder, the accumulated value based on a random bit received from the random bit source when the rounding mode indicates stochastic round; and

employing, by the rounder, a different rounding mode when the rounding mode indicates the different rounding mode.

13. The method of claim 11, the accumulated value is a fixed-point arithmetic value.

14. The method of claim 13, further comprising:

programming a register with a binary point location of the fixed-point arithmetic accumulated value, the binary location specifies a number of fractional bits of the fixed-point arithmetic accumulated value.

15. The method of claim 14, the rounder rounds the accumulated value in response to the NPU aligning the accumulated value to an output representation that has fewer fractional bits than the number of fractional bits programmed into the register.

16. The method of claim 15, further comprising:

programming a second register with a binary point location of the output representation.

17. The method of claim 11, further comprising:

computing each of the plurality of products from first and second operands, and each of the first and second operands is a fixed-point arithmetic value.

18. The method of claim 17, further comprising:

programming a first register with a binary point location of the first operand; and

programming a second register with a binary point location of the second operand.

19. The method of claim 11, each of the plurality of products is a fixed-point arithmetic value.

20. The method of claim 11, further comprising:

generating, by the random bit source, the random bits based on a sampling of random electrical characteristics of an integrated circuit that embodies the neural network unit.

21. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

computer usable program code embodied in said medium, for specifying a neural network unit, the computer usable program code comprising;

first program code for specifying a random bit source that generates random bits; and

second program code for specifying a plurality of neural processing units (NPU), each NPU comprising;

an accumulator into which the NPU accumulates a plurality of products as an accumulated value; and

a rounder that receives the random bits from the random bit source and stochastically rounds the accumulated value based on a random bit received from the random bit source.