APPARATUS EMPLOYING USER-SPECIFIED BINARY POINT FIXED POINT ARITHMETIC

• US 20170102921A1
• Filed: 04/05/2016
• Published: 04/13/2017
• Est. Priority Date: 10/08/2015
• Status: Active Grant

• Current Assignee: Via Alliance Semiconductor Co., Ltd.
• Original Assignee: Via Alliance Semiconductor Co., Ltd.
• Inventors: HENRY, G. GLENN, PARKS, TERRY
• Granted Patent: US 10,228,911 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 5/01 for shifting, e.g. justifying, scaling, normalising digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00
• CPC Class Codes: G06F 7/49942 Significance control
• CPC Class Codes: G06F 7/49947 Rounding
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 9/00 Arrangements for program control, e.g. control units program control for peripheral devices G06F13/10
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06N 3/045 Combinations of networks
• CPC Class Codes: G06N 3/048 Activation functions
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

An apparatus includes a plurality of arithmetic logic units each having an accumulator and an integer arithmetic unit that receives and performs integer arithmetic operations on integer inputs and accumulates integer results of a series of the integer arithmetic operations into the accumulator as an integer accumulated value. A register is programmable with an indication of a number of fractional bits of the integer accumulated values and an indication of a number of fractional bits of integer outputs. A first bit width of the accumulator is greater than twice a second bit width of the integer outputs. A plurality of adjustment units scale and saturate the first bit width integer accumulated values to generate the second bit width integer outputs based on the indications of the number of fractional bits of the integer accumulated values and outputs programmed into the register.

Claims

1. An apparatus, comprising:

a plurality of arithmetic logic units each having;

an accumulator; and

an integer arithmetic unit that receives and performs integer arithmetic operations on integer inputs and accumulates integer results of a series of the integer arithmetic operations into the accumulator as an integer accumulated value;

a register programmable with;

an indication of a number of fractional bits of the integer accumulated values; and

an indication of a number of fractional bits of integer outputs;

a first bit width of the accumulator is greater than twice a second bit width of the integer outputs; and

a plurality of adjustment units that scale and saturate the first bit width integer accumulated values to generate the second bit width integer outputs based on the indications of the number of fractional bits of the integer accumulated values and outputs programmed into the register.

2. The apparatus of claim 1, further comprising:

the adjustment units calculate a difference between the number of fractional bits of the outputs and the number of fractional bits of the integer accumulated values; and

to scale the integer accumulated value, the adjustment units shift the integer accumulated value right by the difference.

3. The apparatus of claim 1, further comprising:

to saturate the integer accumulated value, the adjustment units saturate to maximum/minimum values representable by the second bit width when the right-shifted integer accumulated value is greater/less than the maximum/minimum values representable by the second bit width.

4. The apparatus of claim 1, further comprising:

the accumulator has at least Q bits of storage to store the integer accumulated value; and

Q is a sufficient number of bits to accumulate a series of P of the integer results without loss of precision.

5. The apparatus of claim 4, further comprising:

Q is M plus log₂P, where M is a bit width of the integer results.

6. The apparatus of claim 5, further comprising:

P is a predetermined maximum permissible number of the series of the integer results to generate the integer accumulated value.

7. The apparatus of claim 5, further comprising:

when a bit width of the integer inputs is 8, P is 1023 and Q is 28.

8. The apparatus of claim 5, further comprising:

when a bit width of the integer inputs is 16, P is 511 and Q is 41.

9. The apparatus of claim 1, further comprising:

a memory that hold the integer inputs and provides them to the plurality of arithmetic logic units.

10. The apparatus of claim 9, further comprising:

the plurality of adjustment units write the integer outputs to the memory.

11. The apparatus of claim 1, further comprising:

each of the plurality of arithmetic logic units comprises;

an integer multiplier that performs an integer multiplication of a pair of the integer inputs to generate an integer product; and

an integer adder that performs an integer addition of the integer product and the integer accumulated value to generate an integer sum for storage back into the accumulator.

12. The apparatus of claim 1, each of the plurality of adjustment units further comprising:

a rounder that rounds the integer accumulated values based on the least significant J bits of the integer accumulated value, where J is a difference between the number of fractional bits of the outputs and the number of fractional bits of the integer accumulated values.

13. The apparatus of claim 1, further comprising:

the register is further programmable with a first indicator that indicates whether the data words received from the first memory are signed or unsigned and with a second indicator that indicates whether the weight words received from the second memory are signed or unsigned.

14. The apparatus of claim 1, further comprising:

the integer inputs have a bit width that is the same as the second bit width of the integer outputs.

15. The apparatus of claim 1, further comprising:

the apparatus comprises a neural network unit; and

the adjustment units comprise activation function units that perform an activation function on the scaled and saturated integer accumulated value to normalize it in a non-linear fashion to produce a result that is within a predetermined range of values.

16. A method, comprising:

programming a register with;

an indication of a number of fractional bits of integer accumulated values; and

an indication of a number of fractional bits of integer outputs;

by each of a plurality of arithmetic logic units having an accumulator and an integer arithmetic unit;

performing, by the integer arithmetic unit, integer arithmetic operations on integer inputs; and

accumulating integer results of a series of the integer arithmetic operations into the accumulator as an integer accumulated value;

a first bit width of the accumulator is greater than twice a second bit width of the integer outputs; and

by each of a plurality of adjustment units;

scaling and saturating the first bit width integer accumulated values to generate the second bit width integer outputs based on the indications of the number of fractional bits of the integer accumulated values and outputs programmed into the register.

17. The method of claim 16, further comprising:

calculating, by the adjustment units, a difference between the number of fractional bits of the outputs and the number of fractional bits of the integer accumulated values; and

said scaling the integer accumulated value comprises shifting the integer accumulated value right by the difference.

18. The method of claim 16, further comprising:

said saturating the integer accumulated value comprises saturating to maximum/minimum values representable by the second bit width when the right-shifted integer accumulated value is greater/less than the maximum/minimum values representable by the second bit width.

19. The method of claim 16, further comprising:

the accumulator has at least Q bits of storage to store the integer accumulated value; and

Q is a sufficient number of bits to accumulate a series of P of the integer results without loss of precision.

20. The method of claim 19, further comprising:

Q is M plus log₂P, where M is a bit width of the integer results.

21. The method of claim 16, further comprising:

rounding, by each of the plurality of adjustment units, the integer accumulated values based on the least significant J bits of the integer accumulated value, where J is a difference between the number of fractional bits of the outputs and the number of fractional bits of the integer accumulated values.

22. The method of claim 16, further comprising:

performing, by the adjustment units, an activation function on the scaled and saturated integer accumulated value to normalize it in a non-linear fashion to produce a result that is within a predetermined range of values.

23. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

computer usable program code embodied in said medium, for specifying a neural network unit, the computer usable program code comprising;

first program code for specifying a plurality of arithmetic logic units each having;

an accumulator; and

an integer arithmetic unit that receives and performs integer arithmetic operations on integer inputs and accumulates integer results of a series of the integer arithmetic operations into the accumulator as an integer accumulated value;

second program code for specifying a register programmable with;

an indication of a number of fractional bits of the integer accumulated values; and

an indication of a number of fractional bits of integer outputs;

a first bit width of the accumulator is greater than twice a second bit width of the integer outputs; and

third program code for specifying a plurality of adjustment units that scale and saturate the first bit width integer accumulated values to generate the second bit width integer outputs based on the indications of the number of fractional bits of the integer accumulated values and outputs programmed into the register.