TRANSISTOR AND METHOD FOR FORMING THE SAME

• US 20170104084A1
• Filed: 09/29/2016
• Published: 04/13/2017
• Est. Priority Date: 10/10/2015
• Status: Active Grant

• Current Assignee: Ningbo Semiconductor International Corporation (Semiconductor Manufacturing International Corporation), Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: LI, HAI TING, ZHU, JI GUANG, HUANG, HERB HE, DROWLEY, CLIFFORD IAN
• Granted Patent: US 10,199,478 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76256 using silicon etch back techniques, e.g. BESOI, ELTRAN
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel

Abstract

The present disclosure provides a method for forming a transistor, including: forming a base structure, containing a first gate structure, an active layer covering the first gate structure, and an insulating structure in the active layer; forming a second gate structure on the active layer; forming a source-drain region, including a source region and a drain region in the active layer each on a different side of the second gate structure; and forming a first interlayer dielectric layer covering the base structure and the second gate structure. The method also includes: forming a first contact hole that exposes the first gate structure by etching the first interlayer dielectric layer and the insulating structure; and forming a second contact hole that exposes the second gate structure and a third contact hole that exposes the drain region by etching the first interlayer dielectric layer.

Claims

1. A method for forming a transistor, comprising:

forming a base structure, containing a first gate structure, an active layer covering the first gate structure, and an insulating structure in the active layer;

forming a second gate structure on the active layer;

forming a source-drain region, including a source region and a drain region in the active layer each on a different side of the second gate structure;

forming a first interlayer dielectric layer covering the base structure and the second gate structure;

forming a first contact hole that exposes the first gate structure by etching the first interlayer dielectric layer and the insulating structure;

forming a second contact hole that exposes the second gate structure and a third contact hole that exposes the drain region by etching the first interlayer dielectric layer; and

filling the first contact hole, the second contact hole, and the third contact hole with a conductive material to form a first plug structure, a second plug structure, and a third plug structure, that are aligned along a substantially same direction.

2. The method according to claim 1, wherein forming the base structure comprises:

forming a first substrate, the first substrate containing the active layer, the active layer containing the insulating structure and a well region between two portions of the insulating structure;

forming the first gate structure on the first substrate;

forming a second interlayer dielectric layer covering the first substrate and the first gate structure;

providing a second substrate to be bonded with the second interlayer dielectric layer; and

thinning a back surface of the first substrate to expose the active layer.

3. The method according to claim 2, the first substrate comprising a silicon on insulator (SOI) structure, having a bottom silicon layer, an oxide layer over the silicon bottom layer, and a top silicon layer over the oxide layer, the active layer being in the top silicon layer, wherein:

the first gate structure is formed on the top silicon layer;

the second interlayer dielectric layer covers the top silicon layer and the first gate structure;

the back surface of the first substrate is a surface of the bottom silicon layer facing away from the oxide layer; and

the bottom silicon layer and the oxide layer are removed sequentially to expose the active layer.

4. The method according to claim 3, wherein forming the first substrate includes:

providing the SOI structure;

forming the insulating structure in the top silicon layer; and

performing an ion implantation process on a portion of the top silicon layer between the two portions of the insulating structure.

5. The method according to claim 3, wherein removing the bottom silicon layer and the oxide layer includes:

performing a chemical mechanical polishing (CMP) process to remove a portion of a total thickness of the bottom silicon layer;

using the oxide layer as a thinning-stop layer to perform a wet etching process to remove a remaining portion of the bottom silicon layer;

performing a dry etching process to remove a portion of a total thickness of the oxide layer; and

performing a wet etching process to remove a remaining portion of the oxide layer to expose the active layer.

6. The method according to claim 2, the first substrate comprising a semiconductor substrate, having a first surface containing the active layer, a second surface opposing the first surface, and a thinning-stop layer parallel with the first surface, the active layer being between the thinning-stop layer and the first surface, wherein:

the first gate structure is formed on the first surface of the semiconductor substrate;

the second interlayer dielectric layer covers the first surface and the first gate structure;

the back surface of the first substrate is the second surface of the semiconductor substrate; and

the thinning of the back surface stops at the thinning-stop layer to expose the active layer.

7. The method according to claim 6, wherein forming the first substrate includes:

providing the semiconductor substrate;

forming the insulating structure in the first surface of the semiconductor substrate; and

performing an ion implantation process on a portion of the top silicon layer between the two portions of the insulating structure.

8. The method according to claim 6, wherein thinning the back surface of the semiconductor substrate includes:

performing a CMP process to remove a portion of a total thickness of the semiconductor substrate;

performing a wet etching process to remove a remaining portion of the semiconductor substrate, the wet etching process stopping at the thinning-stop layer; and

removing the thinning-stop layer to expose the active layer.

9. The method according to claim 1, wherein forming the source-drain region includes:

performing a lightly doped drain (LDD) implantation process to form LDDs in the active layer at two sides of the second gate structure;

forming sidewalls on two sides of the second gate structure; and

performing a source-drain ion implantation process to form the source-drain region in the active layer at the two sides of the second gate structure.

10. The method according to claim 1, wherein after forming the source-drain region and before forming the first interlayer dielectric layer, further includes forming a connection layer covering the second gate structure and the source-drain region, wherein:

a bottom of the second contact hole exposes a first connection layer on the second gate structure such that the second plug structure is connected to the second gate structure though the first connection layer; and

a bottom of the third contact hole exposes a second connection layer on one of the drain region and the source region such that the third plug structure is connected to the one of the drain region and the source region through the second connection layer.

11. The method according to claim 1, wherein a thickness of the active layer is less than about 1000 Å

.

12. The method according to claim 9, further including diffusing implanted ions in the source-drain region to a side of the active layer that is closer to the first gate structure.

13. The method according to claim 1, wherein after forming the first contact hole and before forming the first plug structure, the method further includes:

performing an ion implantation along the first contact hole to form a contact hole doped region at a bottom of the first contact hole.

14. The method according to claim 1, wherein the first gate structure includes:

a gate-controlled portion covered by the active layer and the second gate structure; and

a connection portion not covered by the active layer and the second gate structure.

15. The method according to claim 14, wherein a bottom of the first contact hole exposes the first gate structure so that the first plug structure is connected to the connection portion of the first gate structure.

16. A transistor, comprising:

a base structure, containing a first gate structure, an active layer covering the first gate structure, and an insulating structure in the active layer;

a second gate structure on the active layer, the first gate structure and the second gate structure sharing the active layer;

a source-drain region, having a source region and a drain region in the active layer, each on a different side of two sides of the first gate structure and the second gate structure;

a first interlayer dielectric layer covering the base structure and the second gate structure;

a first plug structure, in the first interlayer dielectric layer and the insulating structure, being connected to the first gate structure;

a second plug structure, in the first interlayer dielectric layer, being connected to the second gate structure; and

a third plug structure, in the first interlayer dielectric layer, being connected to the drain region, wherein the first plug structure, the second plug structure, and the third plug structure being aligned along a substantially same direction.

17. The transistor according to claim 16, the first gate structure comprising a gate-controlled portion covered by the active layer and the second gate structure and a connection portion not covered by the active layer and the second gate structure, wherein the first plug structure is connected to the connection portion of the first gate structure.

18. The transistor according to claim 16, wherein a thickness of the active layer is less than about 1000 Å

.

19. The transistor according to claim 16, further comprising:

sidewalls on two sides of the second gate structure; and

lightly doped regions (LDDs) in the active layer on the two sides of the second gate structure, wherein the source region and the drain region each locates on a different side of two sides of the LDDs.

20. The transistor according to claim 16, further comprising a connection layer covering the second gate structure and the drain region.