TECHNIQUES TO PERFORM FORWARD ERROR CORRECTION FOR AN ELECTRICAL BACKPLANE

• US 20170104554A1
• Filed: 11/23/2016
• Published: 04/13/2017
• Est. Priority Date: 01/04/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ganga, Ilango S., Chang, Luke, Belogolovy, Andrey, Ovchinnikov, Andrei
• Granted Patent: US 9,912,442 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: H03M 13/33 Synchronisation based on error coding or decoding
• CPC Class Codes: H03M 13/63 Joint error correction and other techniques H03M13/31 and H03M13/33 take precedence
• CPC Class Codes: H03M 13/6312 Error control coding in combination with data compression
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0042 Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape H04L1/0067 takes precedence
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0047 Decoding adapted to other signal detection operation in conjunction with sequence estimation or equalization H04L25/03286
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0058 Block-coded modulation
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal
• CPC Class Codes: Y02D 30/00 Reducing energy consumption in communication networks

Abstract

Techniques to perform forward error correction for an electrical backplane are described.

Claims

1-20. -20. (canceled)

21. At least one non-transitory machine accessible storage medium having instructions stored thereon, the instructions when executed on a machine, cause the machine to:

receive data from a physical coding sublayer (PCS) of a physical layer, wherein the physical layer comprises a BASE-R physical layer;

use the data to generate an FEC block comprising a shortened cyclic code comprising 32 rows of a particular number of bits, the particular number of bits comprise payload bits generated from output of the PCS and one or more bits of transcoding overhead, wherein the FEC block further comprises 32 parity bits at the end of the FEC block;

scramble the FEC block using a pseudo-noise sequence; and

send the FEC block to a physical medium attachment (PMA) sublayer of the physical layer.

22. The storage medium of claim 21, wherein the data from the PCS comprises 66 bits.

23. The storage medium of claim 22, wherein the data from the PCS further comprises a two-bit synchronization header.

24. The storage medium of claim 21, wherein the pseudo-noise sequence is according to a particular polynomial.

25. The storage medium of claim 24, wherein the pseudo-noise sequence comprises a pseudo-noise sequence of length 2112.

26. The storage medium of claim 25, wherein the particular polynomial comprises r(x)=1+x³⁹+x⁵⁸.

27. An apparatus comprising:

logic, implemented at least in part in hardware circuitry to;

receive data from a physical coding sublayer (PCS) of a physical layer, wherein the physical layer comprises a BASE-R physical layer;

use the data to generate an FEC block comprising a shortened cyclic code comprising 32 rows of a particular number of bits, the particular number of bits comprise payload bits generated from output of the PCS and one or more bits of transcoding overhead, wherein the FEC block further comprises 32 parity bits at the end of the FEC block;

scramble the FEC block using a pseudo-noise sequence; and

send the FEC block to a physical medium attachment (PMA) sublayer of the physical layer.

28. The apparatus of claim 27, wherein the logic comprises an FEC sublayer of the physical layer.

29. The apparatus of claim 28, wherein the FEC sublayer comprises an FEC encoder.

30. The apparatus of claim 29, wherein the FEC sublayer further comprises:

a reverse gearbox;

a compressor to couple to the reverse gearbox;

a selector to couple to the compressor;

a parity generator to couple to the compressor;

a multiplexer to couple to the compressor, the selector, and the parity generator;

a scrambler to couple to the multiplexer; and

a pseudo-noise generator to couple to the scrambler.

31. A method comprising:

receiving data from a physical coding sublayer (PCS) of a physical layer, wherein the physical layer comprises a BASE-R physical layer;

using the data to generate an FEC block comprising a shortened cyclic code comprising 32 rows of a particular number of bits, the particular number of bits comprise payload bits generated from output of the PCS and one or more bits of transcoding overhead, wherein the FEC block further comprises 32 parity bits at the end of the FEC block;

scrambling the FEC block using a pseudo-noise sequence; and

sending the FEC block to a physical medium attachment (PMA) sublayer of the physical layer.

32. The method of claim 31, wherein the data from the PCS comprises 66 bits.

33. The method of claim 32, wherein the data from the PCS further comprises a two-bit synchronization header.

34. The method of claim 31, wherein the pseudo-noise sequence is according to a particular polynomial.

37. A system comprising:

a first device; and

a second device comprising a network interface to couple to the first device over a network, wherein the network interface comprises a physical layer comprising a physical coding sublayer (PCS) and a forward error correction (FEC) sublayer, and the FEC sublayer is to;

receive data from the PCS, wherein the physical layer comprises a BASE-R physical layer;

use the data to generate an FEC block comprising a shortened cyclic code comprising 32 rows of a particular number of bits, the particular number of bits comprise payload bits generated from output of the PCS and one or more bits of transcoding overhead, wherein the FEC block further comprises 32 parity bits at the end of the FEC block;

scramble the FEC block using a pseudo-noise sequence; and

send the FEC block to a physical medium attachment (PMA) sublayer of the physical layer.

38. The system of claim 37, wherein the parity bits are to be generated according to a particular polynomial.

39. The system of claim 38, wherein the particular polynomial comprises g(x)=x³²+x²³+x²¹+x¹¹+x²+1.

40. The system of claim 37, wherein the second device further comprises a media access control (MAC) layer.

41. A system comprising:

means to receive data from a physical coding sublayer (PCS) of a physical layer, wherein the physical layer comprises a BASE-R physical layer;

means to use the data to generate an FEC block comprising a shortened cyclic code comprising 32 rows of a particular number of bits, the particular number of bits comprise payload bits generated from output of the PCS and one or more bits of transcoding overhead, wherein the FEC block further comprises 32 parity bits at the end of the FEC block;

means to scramble the FEC block using a pseudo-noise sequence; and

means to send the FEC block to a physical medium attachment (PMA) sublayer of the physical layer.