CHIP PACKAGE HAVING A PROTECTION PIECE COMPLIANTLY ATTACHED ON A CHIP SENSING SURFACE

• US 20170110416A1
• Filed: 05/20/2016
• Published: 04/20/2017
• Est. Priority Date: 10/15/2015
• Status: Abandoned Application

• Current Assignee: Powertech Technology Inc, Powertech Technology (Suzhou) Ltd.
• Original Assignee: Powertech Technology Inc, Powertech Technology (Suzhou) Ltd.
• Inventors: MIAO, Hong-Yan, HUA, Yi, LIU, Zhi-Ling, JIN, Ruo-Xu
• Application Number:
  US15/160,711
• Publication Number:
  US 20170110416A1
• Time in Patent Office: Days
• CPC Class Codes: G06V 40/1329 Protecting the fingerprint sensor against damage caused by the finger
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92225 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/564 : Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/14618 : Containers
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/37001 : Yield

Abstract

Disclose is a chip package having an adhesive protection piece compliantly attached on the chip sensing surface, comprising a substrate, a main chip disposed on the substrate, an adhesive protection piece covering the main chip and an encapsulant encapsulating the main chip. The main chip has a chip sensing surface facing to a direction away from the substrate and a connection terminal electrically connected to the substrate. The adhesive protection piece essentially consists of a pick-and-place sheet and a die-bonding layer. The encapsulant completely encapsulates the die-bonding layer without covering the external surface of the pick-and-place sheet. The adhesive protection piece is compliantly attached to the chip sensing surface by pick-and-place processes so that the die-bonding layer is attached to the chip sensing surface with a constant adhesive gap. Moreover, the external surface of the pick-and-place sheet is parallel to the chip sensing surface which is not affected by the horizontal deviation of the substrate to resolve the sensing distortion issue when a sensing chip is covered by an adhesive protection piece.

Claims

1. A chip package comprising:

a substrate;

a main chip disposed on the substrate, wherein the main chip has a chip sensing surface and a connecting terminal electrically connected to the substrate;

an adhesive protective piece compliantly attached to the chip sensing surface of the main chip with a constant adhesive gap, the adhesive protective piece having a pick-and-place sheet and a first die-bonding layer, the pick-and-place sheet having an internal surface and an external surface, the first die-bonding layer being disposed between the main chip and the pick-and-place sheet, wherein the external surface of the pick-and-place sheet being parallel to the chip sensing surface is independent from a leveling of the substrate; and

an encapsulant formed on the substrate to encapsulate the main chip, wherein the encapsulant has an encapsulated height corresponding to the substrate greater than the thickness of the main chip but less than a cover height of the external surface of the pick-and-place sheet corresponding to the substrate, wherein the encapsulant encapsulates at least one side of the first die-bonding layer and the external surface of the pick-and-place sheet is exposed from the encapsulant.

2. The chip package as claimed in claim 1, further comprising a second die-bonding layer disposed between the main chip and the substrate, wherein a covered area of the second die-bonding layer is less than a covered area of the first die-bonding layer.

3. The chip package as claimed in claim 2, further comprising at least a minor chip disposed between the main chip and the substrate, wherein the second die-bonding layer encapsulates the minor chip.

4. The chip package as claimed in claim 2, further comprising at least a passive component disposed between the main chip and the substrate, wherein the second die-bonding layer encapsulates the passive component.

5. The chip package as claimed in claim 1, wherein the first die-bonding layer fully covered the internal surface of the pick-and-place sheet with a dimension of the pick-and-place sheet greater than a dimension of the main chip and less than a dimension of the substrate.

6. The chip package as claimed in claim 1, wherein a part of the pick-and-place sheet is encapsulated.

7. The chip package as claimed in claim 1, further comprising a metal cap disposed on the encapsulant and configured to cover the encapsulant, wherein the metal cap has an opening used to expose the external surface of the pick-and-place sheet.

8. The chip package as claimed in claim 7, wherein the substrate and the metal cap are individually coupled to a printed circuit board.

9. The chip package as claimed in claim 1, wherein the connecting terminal is a bonding pad located at a periphery of the chip sensing surface and is electrically connected to the substrate though a bonding wire, wherein a wire loop section of the bonding wire above the main chip is embedded inside the first die-bonding layer.

10. The chip package as claimed in claim 1, wherein the connecting terminal is disposed at a bottom surface of the main chip opposite to the chip sensing surface, wherein the connecting terminal includes at least a bump.

11. The chip package as claimed from claim 1, wherein the chip sensing surface includes a fingerprint sensing area, wherein the first die-bonding layer fully encapsulated the fingerprint sensing area.

12. A chip package comprising:

a substrate;

a main chip disposed on the substrate, the main chip having a chip sensing surface and a connecting terminal electrically connected to the substrate;

an adhesive protective piece disposed on the chip sensing surface of the main chip, the adhesive protective piece having a pick-and-place sheet and a first die-bonding layer disposed between the main chip and the pick-and-place sheet, the pick-and-place sheet having an internal surface and an external surface, wherein the external surface of the pick-and-place sheet being parallel to the chip sensing surface is independent from a leveling of the substrate; and

an encapsulant formed on the substrate configured to encapsulate the main chip and at least one side of the first die-bonding layer, wherein the encapsulant has an encapsulated height corresponding to the substrate greater than a height of the main chip corresponding to the substrate but less than a height of the external surface of the pick-and-place sheet corresponding to the substrate.

13. The chip package as claimed in claim 12, further comprising a second die-bonding layer disposed between the main chip and the substrate, wherein a covered area of the second die-bonding layer is less than a covered area of the first die-bonding layer.

14. The chip package as claimed in claim 13, further comprising at least a minor chip disposed between the main chip and the substrate, wherein the second die-bonding layer encapsulates the minor chip.

15. The chip package as claimed in claim 13, further comprising at least a passive component disposed between the main chip and the substrate, wherein the second die-bonding layer encapsulates the passive component.

16. The chip package as claimed in claim 12, wherein a dimension of the adhesive protective piece is greater than a dimension of the main chip and less than a dimension of the substrate.

17. The chip package as claimed in claim 12, further comprising a metal cap disposed on the encapsulant and configured to cover the encapsulant, the metal cap having a recessed area configured to expose the external surface of the pick-and-place sheet.

18. The chip package as claimed in claim 17, wherein the substrate and the metal cap are individually coupled to a printed circuit board.

19. The chip package as claimed in claim 12, wherein the connecting terminal is a bonding pad disposed on an area around the chip sensing surface and is electrically connected to the substrate though a bonding wire, wherein a part of the bonding wire is embedded inside the first die-bonding layer.

20. The chip package as claimed in claim 12, wherein the connecting terminal is disposed at a bottom surface of the main chip opposite to the chip sensing surface, wherein the connecting terminal includes at least a bump.