INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20170110554A1
• Filed: 07/11/2016
• Published: 04/20/2017
• Est. Priority Date: 10/15/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Tae-jong, Choi, Sung-hyun, Tak, Yong-suk, Park, Gi-gwan, Koo, Bon-young, Park, Ki-yeon
• Granted Patent: US 10,096,688 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/4991 comprising an air gap
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An integrated circuit device includes a fin type active area protruding from a substrate and having an upper surface at a first level; a nanosheet extending in parallel to the upper surface of the fin type active area and comprising a channel area, the nanosheet being located at a second level spaced apart from the upper surface of the fin type active area; a gate disposed on the fin type active area and surrounding at least a part of the nanosheet, the gate extending in a direction crossing the fin type active area; a gate dielectric layer disposed between the nanosheet and the gate; a source and drain region formed on the fin type active area and connected to one end of the nanosheet; a first insulating spacer on the nanosheet, the first insulating spacer covering sidewalls of the gate; and a second insulating spacer disposed between the gate and the source and drain region in a space between the upper surface of the fin type active area and the nanosheet, the second insulating spacer having a multilayer structure.

Claims

1. An integrated circuit device comprising:

a fin type active area protruding from a substrate and having an upper surface at a first level;

a nanosheet extending in parallel to the upper surface of the fin type active area and comprising a channel area, the nanosheet being located at a second level spaced apart from the upper surface of the fin type active area;

a gate disposed on the fin type active area and surrounding at least a part of the nanosheet, the gate extending in a direction crossing the fin type active area;

a gate dielectric layer disposed between the nanosheet and the gate;

a source and drain region formed on the fin type active area and connected to one end of the nanosheet;

a first insulating spacer on the nanosheet, the first insulating spacer covering sidewalls of the gate; and

a second insulating spacer disposed between the gate and the source and drain region in a space between the upper surface of the fin type active area and the nanosheet, the second insulating spacer having a multilayer structure.

2. The integrated circuit device of claim 1,

wherein the gate comprises a main gate portion covering an upper surface of the nanosheet and a sub-gate portion connected to the main gate portion and formed in a space between the fin type active area and the nanosheet,

wherein the first insulating spacer covers sidewalls of the main gate portion, and

wherein the second insulating spacer covers sidewalls of the sub-gate portion.

3. The integrated circuit device of claim 2, wherein the nanosheet is formed in an overlap region covered by the gate in a space between the fin type active area and the gate and has a planar area greater than a planar area of the overlap region.

4. The integrated circuit device of claim 1, wherein the first insulating spacer and the second insulating spacer comprise different materials.

5. The integrated circuit device of claim 1, wherein the second insulating spacer comprises an air space.

11. The integrated circuit device of claim 1, wherein the second insulating spacer comprises:

a first liner comprising one of SiN, SiCN, and SiBN; and

a second liner spaced apart from the gate and the nanowire and comprising one of SiON, SiOCN, and SiBCN, wherein the first liner is between the second liner and the gate and between the second liner and the nanowire.

12. The integrated circuit device of claim 1, wherein the second insulating spacer comprises:

a first liner comprising a first insulating material that does hot comprise oxygen; and

a second liner having a composition different from a composition of the first insulating material and having an oxygen content ranging from 0 to about 50 atom %.

13. The integrated circuit device of claim 1, wherein the second insulating spacer comprises at least one of an air space, SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, and SiO₂.

14. The integrated circuit device of claim 1,

wherein the first insulating spacer comprises SiN, and

wherein the second insulating spacer comprises an insulating layer contacting the source and drain region and comprising SiON.

6-10. -10. (canceled)

15. An integrated circuit device comprising:

a fin type active area protruding from a substrate and extending in a first direction;

at least one nanosheet stack structure facing and spaced apart from an upper surface of the fin type active area, the at least one nanosheet stack structure comprising a plurality of nanosheets each having a channel area;

at least one gate disposed on the fin type active area and covering the at least one nanosheet stack structure, the at least one gate extending in a direction crossing the first direction;

at least one gate dielectric layer disposed between the at least one nanosheet stack structure and the at least one gate;

source and drain regions connected to the plurality of nanosheets; and

insulating spacers each having a multilayer structure and contacting the source and drain regions in spaces between the plurality of nanosheets.

16. The integrated circuit device of claim 15, wherein the at least one gate comprises a main gate portion on the plurality of nanosheets and a sub-gate portion filling the spaces between the plurality of nanosheets, the main gate portion having a first thickness and the sub-gate portion having a second thickness smaller than the first thickness, and

wherein the insulating spacers cover sidewalls of the sub-gate portion.

17. The integrated circuit device of claim 15, wherein the insulating spacers comprise an air space.

18. The integrated circuit device of claim 15, wherein the insulating spacers comprise:

a first liner spaced apart from the source and drain regions and comprising a first insulating material that does not comprise oxygen; and

a second liner contacting the source and drain regions, the second liner having a composition different from a composition of the first insulating material and having an oxygen content ranging from 0 to about 50 atom %.

19. The integrated circuit device of claim 15, wherein the plurality of nanosheets is in at least one overlap region covered by the at least one gate, among spaces between the fin type active area and the at least one gate, and has a planar area greater than a planar area of the at least one overlap region.

20. The integrated circuit device of claim 15, wherein the at least one nanosheet stack structure comprises a plurality of nanosheet stack structures and the at least one gate comprises a plurality of gates, wherein the plurality of nanosheet stack structures are arranged in a line along the first direction on the fin type active area and each comprises a plurality of the nanosheets;

and

wherein the plurality of gates extend in parallel to each other on the fin type active area, the plurality of nanosheet stack structures being arranged between the fin type active area and the plurality of gates.

21-30. -30. (canceled)

31. An integrated circuit device, comprising:

a substrate;

a fin type active area that protrudes from the substrate;

a plurality of source and drain regions on the fin type active area;

a plurality of nanosheets that are adjacent to the plurality of source and drain regions, the plurality of source and drain regions being respectively connected to opposing ends of the plurality of nanosheets; and

a plurality of insulating spacers between ones of the plurality of nanosheets, each of the insulating spacers having a multi-layer structure.

32. The integrated circuit device of claim 31, wherein the multi-layer structure comprises at least one of an air space, SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, and SiO₂.

33. The integrated circuit device of claim 31, further comprising a gate comprising a main gate portion and a plurality of sub-gate portions;

wherein the main gate portion is on the plurality of nanosheets and the plurality of sub-gate portions is between the fin type active area and the plurality of nanosheets.

34. The integrated circuit device of claim 33, wherein the plurality of insulating spacers is a plurality of nanosheet insulating spacers, the integrated circuit device further comprising:

insulating liners on sidewalls of the main gate portion;

gate insulating spacers on sidewalls on the insulating liners; and

protection layers on the insulating liners;

wherein the gate insulating spacers and the nanosheet insulating spacers comprise different materials.

35. The integrated circuit device of claim 33, wherein the multi-layer structure comprises:

a first liner, a second liner, and an air space;

wherein the first liner is between a respective one of the plurality of sub-gate portions, and the second liner and the air space is at least partially limited by the second liner; and

wherein the first liner and the second liner comprise different materials.

36-40. -40. (canceled)