SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20170110576A1
• Filed: 10/11/2016
• Published: 04/20/2017
• Est. Priority Date: 10/14/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: LEE, Jae-Hoon, HA, Tae-Won, KIM, Sung-Soo, PARK, Gi-Gwan, KANG, Sang-Koo, RYU, Koung-Min
• Granted Patent: US 10,177,253 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.

Claims

1. A semiconductor device, comprising:

a gate spacer on a substrate, the gate spacer defining a trench;

a gate electrode filling the trench; and

an interlayer insulating layer on the substrate, the interlayer insulating layer surrounding the gate spacer, the interlayer insulating layer including a first portion having germanium.

2. The semiconductor device of claim 1, wherein a width of the trench is substantially same with increasing distance from the substrate.

3. The semiconductor device of claim 1, wherein a width of the trench decreases with increasing distance from the substrate.

4. The semiconductor device of claim 3, wherein

the gate electrode includes a first sidewall and a second sidewall opposed to each other, and

the first sidewall of the gate electrode and the second sidewall of the gate electrode have slopes at an acute angle with a bottom surface of the gate electrode.

5. The semiconductor device of claim 1, wherein

the gate electrode includes a first sidewall and a second sidewall opposed to each other,

the first sidewall of the gate electrode has a slope at a right angle with a bottom surface of the gate electrode, and

the second sidewall of the gate electrode has a slope at an acute angle with the bottom surface of the gate electrode.

6. The semiconductor device of claim 1, wherein the interlayer insulating layer comprises a second portion which does not include the germanium.

7. The semiconductor device of claim 6, wherein

the interlayer insulating layer includes a lower portion and an upper portion,

the upper portion of the interlayer insulating layer includes the first portion of the interlayer insulating layer, and

the lower portion of the interlayer insulating layer includes the second portion of the interlayer insulating layer, the second portion not including the germanium.

8. The semiconductor device of claim 1, wherein a concentration of the germanium in the first portion of the interlayer insulating layer increases with increasing distance from the substrate.

9. The semiconductor device of claim 1, wherein an upper surface of the interlayer insulating layer and an upper surface of the gate electrode are positioned at a same plane.

10-33. -33. (canceled)

34. A semiconductor device, comprising:

a first gate electrode on a substrate;

a second gate electrode on the substrate, the second gate electrode adjacent to and spaced apart from the first gate electrode;

a pair of first gate spacers at respective sides of the first gate electrode;

a pair of second gate spacers at respective sides of the second gate electrode;

a first interlayer insulating layer on the substrate, the first interlayer insulating layer between one of the pair of first gate spacers and one of the pair of second gate spacers opposing the one of the pair of first gate spacers, a first portion of the first interlayer insulating layer including an oxidized element semiconductor material.

35. The semiconductor device of claim 34, wherein the first portion of the first interlayer insulating layer is an upper portion of the first interlayer insulating layer or a lower portion of the first interlayer insulating layer.

36. The semiconductor device of claim 34, wherein the first portion of the first interlayer insulating layer is an entirety of the first interlayer insulating layer.

37. The semiconductor device of claim 34, wherein the oxidized element semiconductor material includes at least one of germanium (Ge) or silicon (Si).

38. The semiconductor device of claim 34, further including:

a third gate electrode on the substrate;

a fourth gate electrode on the substrate, the fourth gate electrode adjacent to and spaced apart from the third gate electrode;

a pair of third gate spacers at respective sides of the third gate electrode;

a pair of fourth gate spacers at respective sides of the fourth gate electrode;

a second interlayer insulating layer on the substrate, the second interlayer insulating layer between one of the pair of third gate spacers and one of the pair of fourth gate spacers opposing the one of the pair of third gate spacers.

39. The semiconductor device of claim 38, wherein a first portion of the second interlayer insulating layer includes the oxidized element semiconductor material.

40. The semiconductor device of claim 39, wherein an amount of the oxidized element semiconductor material included in the first portion of the first interlayer insulating layer is different from an amount of the oxidized element semiconductor material included in the first portion of the second interlayer insulating layer.

41. The semiconductor device of claim 39, wherein a thickness of the first portion of the first interlayer insulating layer is different from a thickness of the first portion of the second interlayer insulating layer.

42. The semiconductor device of claim 38, wherein the second interlayer insulating layer does not include the oxidized element semiconductor material.

43. The semiconductor device of claim 38, wherein the second gate electrode and the third gate electrode are a same electrode provided between the first gate electrode and the fourth gate electrode.

44. The semiconductor device of claim 38, wherein slopes of the first, second, third, and fourth gate spacers or slopes of sidewalls of the first, second, third, and fourth gate electrodes include both a positive sign and a negative sign.