LC-TANK OSCILLATOR HAVING INTRINSIC LOW-PASS FILTER

• US 20170111009A1
• Filed: 09/11/2016
• Published: 04/20/2017
• Est. Priority Date: 10/14/2015
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Chiu, Wei-Hao, Chueh, Tzu-Chan, Lin, Ang-Sheng
• Granted Patent: US 10,425,038 B2
• Time in Patent Office: Days
• CPC Class Codes: H03B 2200/0082 Lowering the supply voltage and saving power
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/1268 switched inductors

Abstract

An oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors and two N-type transistors. Source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively. Source electrodes of the two N-type transistors are coupled to a supply voltage, gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are coupled to drain electrodes of the two P-type transistors, respectively. In addition, the drain electrodes of the two N-type transistors are coupled to two internal nodes of the inductor.

Claims

1. An oscillator for generating oscillation signals at two output terminals, comprising:

an inductor coupled between the two output terminals;

a capacitor coupled between the two output terminals;

two P-type transistors, wherein source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively; and

two N-type transistors, wherein gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are coupled to drain electrodes of the two P-type transistors, respectively;

wherein the drain electrodes of the two N-type transistors are coupled to two internal nodes of the inductor.

2. The oscillator of claim 1, wherein the capacitor and a portion of the inductor form a low-pass filter for filtering an unwanted frequency component.

3. The oscillator of claim 2, wherein the unwanted frequency component is generated according to another portion of the inductor and a parasitic capacitance.

4. The oscillator of claim 1, further comprising:

a first auxiliary capacitor, coupled between one of the two output terminals and the drain electrode of one of the two N-type transistors.

5. The oscillator of claim 4, wherein the capacitor, the first auxiliary capacitor and a portion of the inductor forma low-pass filter to filter an unwanted frequency component.

6. The oscillator of claim 5, wherein the unwanted frequency component is generated according to another portion of the inductor and a parasitic capacitance.

7. The oscillator of claim 6, wherein a capacitance of the first auxiliary capacitor satisfies an equation:

α

*L*C_PAR=(1−

α

)*L*C_RES, (α

*L) is an inductance of the another portion of the inductor, C_PAR is the parasitic capacitance, ((1−

α

)*L) is an inductance of the portion of the inductor, and C_RES is the capacitance of the first auxiliary capacitor.

8. The oscillator of claim 4, further comprising:

a second auxiliary capacitor, coupled between another one of the two output terminals and the drain electrode of another one of the two N-type transistors.

9. The oscillator of claim 1, further comprising:

a switch module, coupled between the drain electrodes of two N-type transistors and the two internal nodes of the inductor, for selectively connecting the drain electrodes of two N-type transistors to the two internal nodes of the inductor or not.

10. The oscillator of claim 9, wherein the switch module further selectively connects the drain electrodes of two N-type transistors to other two internal nodes of the inductor or not.

11. The oscillator of claim 10, wherein when the oscillator operates in a first mode, the switch module connects the drain electrodes of two N-type transistors to the two internal nodes of the inductor, and not connect the drain electrodes of two N-type transistors to the other two internal nodes of the inductor;

and when the oscillator operates in a second mode, the switch module connects the drain electrodes of two N-type transistors to the other two internal nodes of the inductor, and not connect the drain electrodes of two N-type transistors to the two internal nodes of the inductor.

12. The oscillator of claim 11, wherein the first mode is a Long Term Evolution (LTE) mode, and the second mode is a 2G mode.

13. The oscillator of claim 1, further comprising:

a plurality of gating transistors connected in parallel with the two P-type transistors and the two N-type transistors, respectively, for providing additional current to adjust a transconductance of the oscillator.

14. The oscillator of claim 13, wherein the oscillator operates in a first mode, the gating transistors are turned off;

and when the oscillator operates in a second mode, the gating transistors are turned on.

15. The oscillator of claim 14, wherein the first mode is a Long Term Evolution (LTE) mode, and the second mode is a 2G mode.

16. The oscillator of claim 1, wherein the oscillator is a digitally controlled oscillator (DCO) or a voltage-controlled oscillator (VCO).

17. An oscillator for generating oscillation signals at two output terminals, comprising:

two P-type transistors, wherein source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively;

two N-type transistors, wherein gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are coupled to drain electrodes of the two P-type transistors, respectively; and

a low-pass filter, coupled to the two P-type transistors and the two N-type transistors, for filtering a frequency component of the oscillation signals generated according to a first inductor and a parasitic capacitance.

18. The oscillator of claim 17, wherein the low-pass filter is an inductor-capacitor filter.

19. The oscillator of claim 17, wherein the low-pass filter is formed by a second inductor and a capacitor, and a desired frequency component of the oscillation signals is generated according to the first inductor, the second inductor and the capacitor.