CHOPPER STABILIZED AMPLIFIER

• US 20170111018A1
• Filed: 10/14/2016
• Published: 04/20/2017
• Est. Priority Date: 10/16/2015
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: NOMURA, Naohiro, HORIUCHI, Sachito
• Granted Patent: US 9,899,974 B2
• Time in Patent Office: Days
• CPC Class Codes: H03F 1/02 Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 1/303 using a switching device H03F1/305, H03F3/005, H03F3/38 take precedence
• CPC Class Codes: H03F 1/34 Negative-feedback-circuit arrangements with or without positive feedback H03F1/02 - H03F1/30, H03F1/38 - H03F1/50, H03F3/50 take precedence ; for rejection of common mode signals H03F3/45479
• CPC Class Codes: H03F 2203/45014 the addition of two signals being made in the tail circuit of a differential amplifier for producing the common mode signal
• CPC Class Codes: H03F 2203/45026 One or more current sources are added to the amplifying transistors in the differential amplifier
• CPC Class Codes: H03F 2203/45116 Feedback coupled to the input of the differential amplifier
• CPC Class Codes: H03F 2203/45174 the application of the differential amplifier being in an integrator circuit
• CPC Class Codes: H03F 2203/45444 the CMCL comprising a sample and hold circuit
• CPC Class Codes: H03F 3/005 using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers H03F3/45 takes precedence
• CPC Class Codes: H03F 3/393 with field-effect devices
• CPC Class Codes: H03F 3/45 Differential amplifiers differential sense amplifiers G11C7/062
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/45636 by using feedback means H03F3/45744 takes precedence
• CPC Class Codes: H03F 3/45744 by offset reduction

Abstract

A main amplifier generates an output signal S_OUT according to a difference between first and second voltages VP and VN. A first gm amplifier is arranged as a differential input stage. A second, fully differential, gm amplifier amplifies a voltage difference between its non-inverting and inverting input terminals, and outputs a differential current signal I_3N/I_3P via its inverting and non-inverting output terminals. An integrator integrates a differential input current I_4P/I_4N input via its non-inverting and inverting input terminals, and samples and holds the signal every predetermined period, to generate a differential voltage signal. A first selector is arranged as an upstream stage of the second gm amplifier, and outputs the differential input signal without change or otherwise after swapping. A second selector is arranged as a downstream stage of the second gm amplifier, and outputs the signal I_3N/I_3P output from the second gm amplifier without change or otherwise after swapping.

Claims

1. A chopper stabilized amplifier comprising:

a non-inverting input pin that receives a first voltage;

an inverting input pin that receives a second voltage;

a main amplifier that generates an output signal according to a difference between the first voltage and the second voltage; and

a correction circuit,

wherein the main amplifier comprises;

a differential input stage that generates a first current signal, wherein the differential input stage includes a first gm amplifier having a non-inverting input terminal connected to the non-inverting input pin and an inverting input terminal connected to the inverting input pin; and

an output stage that receives the first current signal so as to generate the output signal of the main amplifier,

wherein the correction circuit comprises;

a second gm amplifier configured as a fully differential amplifier that amplifies a voltage difference between its non-inverting input terminal and its inverting input terminal, so as to output a differential current signal from its inverting output terminal and its non-inverting output terminal;

an integrating circuit that integrates a differential input current input to its non-inverting input terminal and its inverting input terminal, that samples and holds the current integrated for a predetermined period, and that generates a differential voltage signal;

a first selector arranged as an upstream stage of the second gm amplifier, so as to switch a state between;

(i) a first state in which the non-inverting input pin and the inverting input pin are respectively connected to the inverting input terminal and the non-inverting input terminal of the second gm amplifier; and

(ii) a second state in which the non-inverting input pin and the inverting input pin are respectively connected to the non-inverting input terminal and the inverting input terminal of the second gm amplifier;

a second selector arranged downstream from the second gm amplifier, so as to switch a state between;

(i) a first state in which the inverting output terminal and the non-inverting output terminal of the second gm amplifier are respectively connected to the inverting input terminal and the non-inverting input terminal of the integrating circuit; and

(ii) a second state in which the inverting output terminal and the non-inverting output terminal of the second gm amplifier are respectively connected to the non-inverting input terminal and the inverting input terminal of the integrating circuit; and

a third gm amplifier that converts the differential voltage signal generated by the integrating circuit into a second current signal, and that superimposes the second current signal on the first current signal.

2. The chopper stabilized amplifier according to claim 1, wherein the integrating circuit comprises:

an integrator that integrates a differential input current input to the non-inverting input terminal and the inverting input terminal, so as to generate a differential voltage signal; and

a sample-and-hold circuit that samples and holds the differential voltage signal generated by the integrator.

3. The chopper stabilized amplifier according to claim 1, wherein each of the first gm amplifier and the third gm amplifier is configured as a fully differential amplifier,

and wherein the second current signal configured as a differential signal is superimposed on the second current signal configured as a differential signal.

4. The chopper stabilized amplifier according to claim 1, wherein each of the first selector and the second selector is controlled according to a first clock signal.

5. The chopper stabilized amplifier according to claim 4, wherein the integrating circuit is controlled such that the integrating circuit is set to a hold state at an edge timing of the first clock signal.

6. The chopper stabilized amplifier according to claim 4, wherein the integrating circuit is controlled such that the integrating circuit performs a sampling operation in a period in which the first clock is stable.

7. The chopper stabilized amplifier according to claim 5, wherein the integrating circuit is controlled according to a second clock signal,

and wherein edges of the first clock signal are shifted from edges of the second clock signal.

8. The chopper stabilized amplifier according to claim 7, wherein the second clock signal has a period T_B which is an integer multiple of a period of the first clock signal.

9. The chopper stabilized amplifier according to claim 8, wherein the second clock signal has a period T_B that is twice the period of the first clock signal.

10. The chopper stabilized amplifier according to claim 9, wherein each edge of the second clock is shifted by ⅛

of the period thereof T_B/8 with respect to an edge of the first clock signal.

11. The chopper stabilized amplifier according to claim 1, wherein the second gm amplifier comprises a first transistor and a second transistor, each of which is configured as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor),

wherein a source of each of the first transistor and the second transistor is connected to a common tail current source,

and wherein the second gm amplifier outputs currents that respectively flow through the first transistor and the second transistor.

12. The chopper stabilized amplifier according to claim 2, wherein the integrator comprises:

a third MOSFET having a source connected to a fixed voltage line and a gate receiving one component of a differential current signal output from the second selector;

a fourth MOSFET having a source connected to the fixed voltage line and a gate receiving the other component of the differential current signal output from the second selector;

a first capacitor arranged between the gate and a drain of the third MOSFET; and

a second capacitor arranged between the gate and a drain of the fourth MOSFET.

13. The chopper stabilized amplifier according to claim 2, further comprising a common mode feedback circuit that adjusts a bias state of the second gm amplifier such that an intermediate voltage between two output voltages of the integrator approaches a target voltage.

14. The chopper stabilized amplifier according to claim 1, further comprising:

a third capacitor arranged between a first output terminal of the first selector and one input terminal of the second gm amplifier; and

a fourth capacitor arranged between a second output terminal of the first selector and the other input terminal of the second gm amplifier.

15. The chopper stabilized amplifier according to claim 2, wherein each of the first selector and the sample-and-hold circuit comprises a plurality of CMOS switches,

and wherein each of the plurality of CMOS switches included in the first selector is smaller than each of the plurality of CMOS switches included in the sample-and-hold circuit.

16. The chopper stabilized amplifier according to claim 1, wherein each of the first selector and the second selector comprises a plurality of CMOS switches,

and wherein each of the plurality of CMOS switches included in the first selector is smaller than each of the plurality of CMOS switches included in the second selector.

17. The chopper stabilized amplifier according to claim 1, wherein the first selector comprises a plurality of CMOS switches,

and wherein each of the plurality of CMOS switches comprises a P-channel MOSFET and an N-channel MOSFET, each of which is configured such that a product of a channel width W and a channel length L thereof is smaller than 1 μ

m².

18. The chopper stabilized amplifier according to claim 17, wherein each CMOS switch comprises a P-channel MOSFET and an N-channel MOSFET, each of which has the same size.

19. The chopper stabilized amplifier according to claim 7, further comprising a frequency divider circuit that divides a frequency of the first clock signal so as to generate the second clock signal,

wherein the frequency divider circuit comprises a D flip-flop,

wherein the D flip-flop comprises a plurality of CMOS switches,

and wherein, among the CMOS switches, a part that is arranged between an input terminal and an output terminal of the D flip-flop comprises an N-channel MOSFET having a channel length that is greater than a channel length of an N-channel MOSFET of the other part that is arranged in a different region of the D flip-flop.

20. The chopper stabilized amplifier according to claim 1, monolithically integrated on a single semiconductor substrate.