PHASE AND AMPLITUDE DETECTION IN WIRELESS ENERGY TRANSFER SYSTEMS

• US 20170111029A1
• Filed: 10/12/2016
• Published: 04/20/2017
• Est. Priority Date: 10/14/2015
• Status: Active Grant

• Current Assignee: WiTricity Corporation
• Original Assignee: WiTricity Corporation
• Inventors: Karnstedt, Curt
• Granted Patent: US 9,929,721 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 19/25 using digital measurement techniques
• CPC Class Codes: G01R 23/167 with digital filters
• CPC Class Codes: G01R 25/00 Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
• CPC Class Codes: G01R 25/04 involving adjustment of a phase shifter to produce a predetermined phase difference, e.g. zero difference
• CPC Class Codes: H02J 50/12 of the resonant type
• CPC Class Codes: H03H 17/0045 Impedance matching networks
• CPC Class Codes: H03H 17/02 Frequency selective networks digital computers for complex mathematical operations G06F17/10

Abstract

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for detecting characteristics of an input signal. One aspect includes a first finite input response (FIR) filter, a second FIR filter, and a controller coupled with the first and second FIR filters. The first FIR filter receives an input signal and a first reference signal. The first FIR filter filters the first reference signal to generate a first sinusoidal signal and mixes the first sinusoidal signal and the input signal to generate a first mixed signal. The second FIR filter receives the input signal and a second reference signal. The second FIR filter filters the second reference signal to generate a second sinusoidal signal and mixes the second sinusoidal signal and the input signal to generate a second mixed signal. The controller determines characteristics of the input signal based on the first and second mixed signals.

Claims

1. An electronic device comprising:

a first finite input response (FIR) filter that receives an input signal and a first reference signal, wherein the first FIR filter filters the first reference signal to generate a first sinusoidal signal and mixes the first sinusoidal signal and the input signal to generate a first mixed signal;

a second FIR filter that receives the input signal and a second reference signal, wherein the second FIR filter filters the second reference signal to generate a second sinusoidal signal and mixes the second sinusoidal signal and the input signal to generate a second mixed signal; and

a controller coupled with the first FIR filter and the second FIR filter, the controller configured to determine a characteristic of the input signal based on the first mixed signal and the second mixed signal.

2. The electronic device of claim 1, wherein the characteristic of the input signal is a phase or an amplitude of the input signal.

3. The electronic device of claim 1, wherein the characteristic of the input signal includes both a phase and an amplitude of the input signal.

4. The electronic device of claim 1, wherein the first and second reference signals are square waves.

5. The electronic device of claim 4, wherein the square waves are time-sampled square waves.

6. The electronic device of claim 5, wherein a sampling rate of the square waves is twelve times a fundamental frequency of the square wave.

7. The electronic device of claim 5, wherein the first reference signal is phase shifted with respect to the second reference signal by a predetermined number of samples.

8. The electronic device of claim 4, wherein each of the first and the second FIR filter comprises a plurality of filter zeros, and the filter zeros are selected to cancel harmonic frequencies of the first or second reference signal.

9. The electronic device of claim 8, wherein zeros of each of the first and the second FIR filter are selected to cancel third, fifth, seventh, and ninth harmonics of the first or second reference signal.

10. The electronic device of claim 1, wherein each of the first and the second FIR filter comprises a plurality of filter taps, each filter tap comprising:

a delay circuit;

a switch; and

a resistor electrically connected to a terminal of the switch,

wherein one of the first or the second reference signal is applied to an input of the delay circuit,

wherein the switch is controlled by an output of the delay circuit, and

wherein the input signal passes through the switch.

11. The electronic device of claim 10, wherein values for the resistors of the plurality of filter taps for each of the first and second FIR filters represent filter zeros that are selected to cancel harmonic frequencies of the first or second reference signal.

12. The electronic device of claim 10, wherein each of the first and the second FIR filters comprises five filter taps.

13. The electronic device of claim 1, wherein determining the phase of the input signal comprises determining an arctangent of a quotient of the second mixed signal divided by the first mixed signal.

14. The electronic device of claim 1, further comprising:

a first filter coupled with the first FIR filter and the controller, wherein the first filter filters the first mixed signal such that the first mixed signal is a direct current (DC) signal; and

a second filter coupled with the second FIR filter and the controller, wherein the second filter filters the second mixed signal such that the second mixed signal is a DC signal.

15. The electronic device of claim 1, wherein the controller is one of:

a microcontroller, a computer processor, a field programmable logic array (FPGA), or an application specific integrated circuit (ASIC).

16. The electronic device of claim 1, wherein the controller is further configured to provide data indicating the phase of the input signal to an impedance matching network.

17. The electronic device of claim 1, further comprising:

an impedance matching network coupled with the controller, wherein the impedance matching network is configured to receive data indicating the phase of the input signal from the controller and adjust an impedance value of a resonator in accordance with the received data.

18. The electronic device of claim 1, further comprising:

a third FIR filter that receives a second input signal and the first reference signal, wherein the third FIR filter filters the first reference signal to generate a first sinusoidal signal and mixes the first sinusoidal signal and the second input signal to generate a third mixed signal;

a fourth FIR filter that receives the second input signal and the second reference signal, wherein the fourth FIR filter filters the second reference signal to generate a second sinusoidal signal and mixes the second sinusoidal signal and the second input signal to generate a fourth mixed signal;

wherein the controller is coupled with the third FIR filter and the fourth FIR filter and configured to;

determine a phase of the second input signal based on the third mixed signal and the fourth mixed signal, and

determine a phase difference between the input signal and the second input signal.

19. A finite impulse response (FIR) filter comprising:

a plurality of filter taps, each filter tap comprising;

a delay circuit comprising an input terminal to receive a square wave and an output terminal to output a delayed version of the square wave;

a switch comprising an input terminal, an output terminal, and a control terminal, the control terminal being electrically connected to the output terminal of the delay circuit to receive the delayed version of the square wave at the control terminal, and the input terminal of the switch being electrically connected to a common input signal line for the plurality of filter taps; and

a resistor electrically connected to one of the input terminal or the output terminal of the switch;

an operational amplifier, wherein an output terminal of each of the plurality of filter taps is electrically connected to an input terminal of the operational amplifier; and

a feedback path electrically connecting an output terminal of the operational amplifier to the input terminal of the operational amplifier.

20. The FIR filter of claim 19, wherein values for the resistors of the plurality of filter taps represent filter zeros that are selected to cancel harmonic frequencies of the square wave.

21. The FIR filter of claim 20, wherein the filter zeros are selected to cancel the third, fifth, seventh, ninth harmonics of the square wave.

22. The FIR filter of claim 19, wherein an output signal of the operation amplifier is a mixed signal comprising an input signal mixed with a sinusoidal signal at a fundamental frequency of the square wave.

23. The FIR filter of claim 22, wherein the common input signal is a direct current (DC) signal and the output signal of the operational amplifier is the sinusoidal signal at a fundamental frequency of the square wave.

24. The FIR filter of claim 19, wherein each delay circuit of the plurality of filter taps comprises a flip-flop.