TEST PARTITION EXTERNAL INPUT/OUTPUT INTERFACE CONTROL

• US 20170115338A1
• Filed: 10/27/2016
• Published: 04/27/2017
• Est. Priority Date: 10/27/2015
• Status: Active Application

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Chadalavda, Sailendra, Sarangi, Shantanu, Colburn, Jonathon E., Smith, Dan, Wu, Jue, Yilmaz, Mahmut, Sonawane, Milind, Sanghani, Amit
• Granted Patent: US 10,281,524 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/2607 Circuits therefor G01R31/2642 takes precedence
• CPC Class Codes: G01R 31/2803 by means of functional tests, e.g. logic-circuit-simulation or algorithms therefor testing electronic digital computers G06F11/00
• CPC Class Codes: G01R 31/2806 Apparatus therefor, e.g. test stations, drivers, analysers, conveyors G01R31/2805, G01R31/281, G01R31/2818 take precedence
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

In one embodiment, a test system comprises: a test partition configured to perform test operations; a centralized test controller for controlling testing by the test partition; and a test link interface controller configured to communicate between the centralized test controller and the test partition, wherein the test link interface controller controls dynamic changes to external pads associated with the test operations. The test link interface controller dynamically selects between an input direction and output direction for the external pads. The test link interface includes a pin direction controller that generates direction control signals based on the state of local test controller and communicates the desired direction to a boundary scan cell associated with the pin. The boundary scan cell programs the pad to either input or output direction depending on direction control signals. The input direction corresponds to driving test data and the output direction corresponds to observing test data.

Claims

1. A chip test system comprising:

a test partition configured to perform test operations;

a centralized test controller for controlling testing by the test partition; and

a test link interface controller configured to communicate between the centralized test controller and the test partition, wherein the test link interface controller controls dynamic changes to external pads associated with the test operations.

2. The chip test system of claim 1, wherein the test link interface controller dynamically selects between an input direction and output direction for the external pads.

3. The chip test system of claim 1, wherein the test link interface comprises a pin direction controller that generates direction control signals based on the state of local test controller and communicates the desired direction to a boundary scan cell associated with the pin.

4. The chip test system of claim 3, wherein the boundary scan cell programs the pad to either an input or an output direction depending on the direction control signals.

5. The chip test system of claim 1, wherein the input direction corresponds to driving test data and the output direction corresponds to observing test data.

6. The chip test system of claim 1, wherein test control and test output connections are pipelined similarly so that test data and control are in sync and connections in the test link interface and external pads switch to an indicated direction by the time input/output data is ready.

7. The chip test system of claim 1, wherein an IO subsystem of the test link interface is dedicated to a partition.

8. A chip test method comprising:

receiving information regarding testing characteristics;

analyzing the information regarding the testing characteristics; and

controlling a direction of information communication on a set of external pads in accordance with the analysis of the testing characteristics.

9. The chip test method of claim 8, wherein a test link interface performs the controlling of the direction of information communication.

10. The chip test method of claim 9, wherein the test link interface is a standard and consistent design for multiple circuit designs.

11. The chip test method of claim 9, wherein the test link interface enables reduced pin count test as compared to separate dedicated input pads and dedicated output pads.

12. The chip test method of claim 9, wherein the test link interface enables multi-site testing in accordance with TSV pin limitations.

13. The chip test method of claim 9, wherein the test link interface facilitates communication of information in accordance with a granular dynamic test process, wherein the granular dynamic test process comprises:

communicating test information internally in accordance with a first set of test connections;

communicating the test information externally in accordance with a second set of test connections; and

converting between signals on the first set of test connections and signals on the a second set of test connections, wherein the converting comprises controlling dynamic changes to the external pads.

14. The chip test method of claim 13, wherein the converting enables circuit design and test pattern reuse.

15. A chip test system comprising:

a plurality of functional components arranged in test partitions;

a plurality of scan test chains configured to perform testing of the plurality of functional components, wherein plurality of scan test chains utilize a first set of test signal connections;

a centralized test controller for controlling testing by the scan test chains; and

a test link interface configured to coordinate communication between the centralized test controller and external bi-directional pads.

16. The chip test system of claim 15, wherein the connections are implemented in RTL as they are predetermined and decoupled from the a generic design for the test partitions, wherein the implementation in RTL enables early verification.

17. The chip test system of claim 15, wherein an Input/Output (IO) subsystem of the test link interface is a dedicated point-to-point test link to at least one of the test partitions.

18. The chip test system of claim 15, wherein an Input/Output (IO) subsystem of the test link interface includes a shared link between multiple test partitions.

19. The system of claim 15, wherein the fast interface comprises single pin control for at least one of the test partitions, wherein the test partition includes a test pipeline and dynamic standard test access.

20. The system of claim 15, wherein the test link interface is a standard and consistent interface for the test partitions within a single chip and across multiple chips.