METHOD AND SYSTEM FOR DYNAMIC STANDARD TEST ACCESS (DSTA) FOR A LOGIC BLOCK REUSE

• US 20170115345A1
• Filed: 10/27/2016
• Published: 04/27/2017
• Est. Priority Date: 10/27/2015
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Nelapatla, Bala Tarun, Kumar reddy.S, Rajendra, Sonawane, Milind, Sanghani, Amit, Sarangi, Shantanu, Colburn, Jonathon E., Chadalavda, Sailendra, Yilmaz, Mahmut
• Granted Patent: US 10,451,676 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/2607 Circuits therefor G01R31/2642 takes precedence
• CPC Class Codes: G01R 31/2803 by means of functional tests, e.g. logic-circuit-simulation or algorithms therefor testing electronic digital computers G06F11/00
• CPC Class Codes: G01R 31/2806 Apparatus therefor, e.g. test stations, drivers, analysers, conveyors G01R31/2805, G01R31/281, G01R31/2818 take precedence
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

A method for testing. An external clock frequency is generated. Test data is supplied over a plurality of SSI connections clocked at the external clock frequency, wherein the test data is designed for testing a logic block. A DSTA module is configured for the logic block that is integrated within a chip to a bandwidth ratio, wherein the bandwidth ratio defines the plurality of SSI connections and a plurality of PSI connections of the chip. The external clock frequency is divided down using the bandwidth ratio to generate an internal clock frequency, wherein the bandwidth ratio defines the external clock frequency and the internal clock frequency. The test data is scanned over the plurality of PSI connections clocked at the internal clock frequency according to the bandwidth ratio, wherein the plurality of PSI connections is configured for inputting the test data to the plurality of scan chains.

Claims

1. A method for testing, comprising:

generating a first external clock frequency;

supplying test data over a first plurality of serial scan input (SSI) connections clocked at said first external clock frequency, wherein said test data is designed for testing a logic block when input to a plurality of scan chains of said logic block;

configuring a Dynamic Standard Test Access (DSTA) module for said logic block that is integrated within a first chip to a first bandwidth ratio, wherein said first bandwidth ratio defines said first plurality of SSI connections and a first plurality of pseudo scan input (PSI) connections of said logic block;

dividing said first external clock frequency down using said first bandwidth ratio to generate a first internal clock frequency, wherein said first bandwidth ratio also defines said first external clock frequency and said first internal clock frequency; and

scanning said test data over said first plurality of PSI connections clocked at said first internal clock frequency according to said first bandwidth ratio, wherein said first plurality of PSI connections is configured for inputting said test data to said plurality of scan chains.

2. The method of claim 1, wherein said scanning said test data comprises:

collecting said test data over a first number of external clock cycles, wherein said first bandwidth ratio also defines said first number of external clock cycles at said first external clock frequency and a first number of internal clock cycles at said first internal clock frequency; and

scanning said test data over said first plurality of PSI connections over said first number of internal clock cycles.

3. The method of claim 2, wherein said first number of internal clock cycles is one.

4. The method of claim 1, wherein said scanning said test data comprises:

for each SSI connection, collecting a corresponding first subset of test data over a first number of external clock cycles, wherein said first bandwidth ratio also defines said first number of external clock cycles at said first external clock frequency and a first number of internal clock cycles at said first internal clock frequency; and

scanning said corresponding first subset of test data over a corresponding first number of PSI connections over said first number of internal clock cycles at said internal clock frequency, wherein said first bandwidth ratio defines said first number of PSI connections.

5. The method of claim 1, further comprising:

configuring said DSTA module for said logic block that is integrated within a second chip to a second bandwidth ratio, wherein said second bandwidth ratio defines a second plurality of SSI connections and a second plurality of PSI connections, wherein said second plurality of SSI connections is configured for receiving said test data clocked at a second external clock frequency, and wherein said second plurality of PSI connections is configured for inputting said test data to said plurality of scan chains according to said second bandwidth ratio, wherein said second bandwidth ratio also defines said second external clock frequency and said second internal clock frequency.

6. The method of claim 5, wherein said first plurality of PSI connections is identical to said second plurality of PSI connections.

7. The method of claim 1, further comprising:

adjusting said first external clock frequency to match said first bandwidth ratio, wherein said internal clock frequency is fixed.

8. The method of claim 1, further comprising:

adjusting said internal clock frequency to match said first bandwidth ratio, wherein said external clock frequency is fixed.

9. The method of claim 1, further comprising:

receiving output data from said plurality of scan chains over a first plurality of pseudo scan output (PSO) connections and clocked at said internal clock frequency; and

scanning said output data over a plurality of serial scan output (SSO) connections clocked at said first external clock frequency.

10. The method of claim 9, wherein said first plurality of SSI connections comprises at least one of said first plurality of SSO connections.

11. The method of claim 9, further comprising:

wherein in said receiving output data, said first bandwidth ratio also defines said first plurality of PSO connections and a first plurality of serial scan output (SSO) connections; and

wherein in said scanning said output data, said output data is scanned according to said first bandwidth ratio, such that said output data is collected from said first plurality of PSO connections over said first number of internal clock cycles at said first internal clock frequency, and scanned over said first plurality of SSO connections over said first number of external clock cycles at said first external clock frequency.

12. The method of claim 1, further comprising:

broadcasting said test data over a super plurality of SSI connections clocked at said first external clock frequency, wherein said super plurality of SSI connections comprises said first plurality of SSI connections for testing said first logic block and another plurality of SSI connections configured for testing another logic block similarly as said first logic block.

13. A computer system comprising:

a processor; and

memory coupled to said processor and having stored therein instructions that, if executed by said computer system, cause said computer system to execute a method for testing comprising;

generating a first external clock frequency;

supplying test data over a first plurality of serial scan input (SSI) connections clocked at said first external clock frequency, wherein said test data is designed for testing a logic block when input to a plurality of scan chains of said logic block;

configuring a Dynamic Standard Test Access (DSTA) module for said logic block that is integrated within a first chip to a first bandwidth ratio, wherein said first bandwidth ratio defines said first plurality of SSI connections and a first plurality of pseudo scan input (PSI) connections of said first chip;

dividing said first external clock frequency down using said first bandwidth ratio to generate a first internal clock frequency, wherein said first bandwidth ratio also defines said first external clock frequency and said first internal clock frequency; and

scanning said test data over said first plurality of PSI connections clocked at said first internal clock frequency according to said first bandwidth ratio, wherein said first plurality of PSI connections is configured for inputting said test data to said plurality of scan chains.

14. The computer system of claim 13, wherein said scanning said test data in said method further comprises:

collecting said test data over a first number of external clock cycles, wherein said first bandwidth ratio also defines said first number of external clock cycles at said first external clock frequency and a first number of internal clock cycles at said first internal clock frequency; and

scanning said test data over said first plurality of PSI connections over said first number of internal clock cycles.

15. The computer system of claim 13, wherein said method further comprises:

configuring said DSTA module for said logic block integrated within a second chip to a second bandwidth ratio, wherein said second bandwidth ratio defines a second plurality of SSI connections and a second plurality of PSI connections of said second chip, wherein said second plurality of SSI connections is configured for receiving said test data clocked at a second external clock frequency, and wherein said second plurality of PSI connections is configured for inputting said test data to said plurality of scan chains according to said second bandwidth ratio, wherein said second bandwidth ratio also defines said second external clock frequency and said second internal clock frequency.

16. The computer system of claim 13, wherein said method further comprises:

receiving output data from said plurality of scan chains over a first plurality of pseudo scan output (PSO) connections and clocked at said internal clock frequency; and

scanning said output data over a plurality of serial scan output (SSO) connections clocked at said first external clock frequency.

17. An apparatus for testing comprising:

an external clock for generating a first external clock frequency;

a first plurality of serial scan input (SSI) connections of an automatic test equipment (ATE) configured for supplying test data clocked at said first external clock frequency, wherein said test data is designed for testing a logic block when input to a plurality of scan chains of said logic block;

a Dynamic Standard Test Access (DSTA) module for said logic block that is integrated within a first chip, wherein said DSTA module is configured to a first bandwidth ratio, wherein said first bandwidth ratio defines said first plurality of SSI connections and a first plurality of pseudo scan input (PSI) connections of said first chip;

a clock divider configured for dividing said first external clock frequency down using said first bandwidth ratio to generate a first internal clock frequency, wherein said first bandwidth ratio also defines said first external clock frequency and said first internal clock frequency; and

a serializer for scanning said test data over said first plurality of PSI connections clocked at said first internal clock frequency according to said first bandwidth ratio, wherein said first plurality of PSI connections is configured for inputting said test data to said plurality of scan chains.

18. The apparatus of claim 17, wherein said serializer is configured for:

collecting said test data over a first number of external clock cycles, wherein said first bandwidth ratio also defines said first number of external clock cycles at said first external clock frequency and a first number of internal clock cycles at said first internal clock frequency; and

scanning said test data over said first plurality of PSI connections over said first number of internal clock cycles.

19. The apparatus of claim 17, further comprising:

said DSTA module for said logic block integrated within a second chip that is configured to a second bandwidth ratio, wherein said second bandwidth ratio defines a second plurality of SSI connections and a second plurality of PSI connections of said second chip, wherein said second plurality of SSI connections is configured for receiving said test data clocked at a second external clock frequency, and wherein said second plurality of PSI connections is configured for inputting said test data to said plurality of scan chains according to said second bandwidth ratio, wherein said second bandwidth ratio also defines said second external clock frequency and said second internal clock frequency.

20. The apparatus of claim 17, further comprising:

a deserializer configured for receiving output data from said plurality of scan chains over a first plurality of pseudo scan output (PSO) connections and clocked at said internal clock frequency, and configured for scanning said output data over a plurality of serial scan output (SSO) connections clocked at said first external clock frequency.