SCAN SYSTEM INTERFACE (SSI) MODULE
First Claim
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1. A computer system comprising:
- a processor; and
memory coupled to said processor and having stored therein instructions that, if executed by said computer system, cause said computer system to execute a method for testing comprising;
sending an instruction to a JTAG controller to select a first internal test data register of a plurality of data registers;
programming said first internal test data register to configure mode control access and state control access for a test controller implementing a sequential scan architecture at a system level.
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Abstract
A method for testing. The method includes sending a single instruction over a JTAG interface to a JTAG controller to select a first internal test data register of a plurality of data registers. The method includes programming the first internal test data register using the JTAG interface to configure mode control access and state control access for a test controller implementing a sequential scan architecture to test a chip at a system level.
29 Citations
20 Claims
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1. A computer system comprising:
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a processor; and memory coupled to said processor and having stored therein instructions that, if executed by said computer system, cause said computer system to execute a method for testing comprising; sending an instruction to a JTAG controller to select a first internal test data register of a plurality of data registers; programming said first internal test data register to configure mode control access and state control access for a test controller implementing a sequential scan architecture at a system level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A non-transitory computer-readable medium having computer-executable instructions for causing a computer system to perform a method for discovering wireless access comprising:
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sending an instruction to a JTAG controller to select a first internal test data register of a plurality of data registers; programming said first internal test data register to configure mode control access and state control access for a test controller implementing a sequential scan architecture at a system level. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method for testing, comprising:
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sending a single instruction over a JTAG interface to a JTAG controller to select a first internal test data register of a plurality of data registers; programming said first internal test data register using said JTAG interface to configure mode control access and state control access for a test controller implementing a sequential scan architecture to test a chip at a system level. - View Dependent Claims (18, 19, 20)
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Specification