DYNAMIC INDEPENDENT TEST PARTITION CLOCK
First Claim
1. A chip test system comprising:
- a plurality of test partitions, wherein at least one of the plurality of test partitions comprises;
a partition test interface controller configured to control testing within the at least one test partition in accordance with dynamic selection of a test mode, wherein the dynamic selection of the test mode and control of testing within the at least one of the plurality of test partitions is independent of selection of a test mode and control in others of the plurality of test partitions; and
a test chain configured to perform test operations, the test scan test chain coupled to the partition test interface controller; and
a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins.
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Accused Products
Abstract
In one embodiment, a test system comprises: a plurality of test partitions and a centralized controller configured to coordinate testing between the plurality of test partitions. At least one of the plurality of test partitions comprises: a partition test interface controller configured to control testing within at least one test partition in accordance with dynamic selection of a test mode, and at least one test chain configured to perform test operations. The dynamic selection of the test mode and control of testing within a test partition can be independent of selection of a test mode and control in others of the plurality of test partitions. In one embodiment, a free running clock signal is coupled to a test partition, and the partition test mode controller transforms the free running clock signal into a local partition test clock which is controlled in accordance with the dynamic selection of the test mode.
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Citations
20 Claims
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1. A chip test system comprising:
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a plurality of test partitions, wherein at least one of the plurality of test partitions comprises; a partition test interface controller configured to control testing within the at least one test partition in accordance with dynamic selection of a test mode, wherein the dynamic selection of the test mode and control of testing within the at least one of the plurality of test partitions is independent of selection of a test mode and control in others of the plurality of test partitions; and a test chain configured to perform test operations, the test scan test chain coupled to the partition test interface controller; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of testing different partitions of a chip in independent test modes, the method comprising:
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accessing a test mode selection for a first partition; controlling testing of said first partition in accordance with said test mode selection for said first partition independent of a test mode selection for a second partition; and performing test operations in said first partition in accordance with said controlling. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A test system comprising:
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a first test partition configured to execute a first test pattern; a second test partition configured to execute a second test pattern, wherein the second test partition executes at least a portion of the second test pattern in parallel with execution of at least a portion of the first test pattern on the first test partition, and the portion of the second test pattern and the portion of the first test pattern are associated with different test modes; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. - View Dependent Claims (18, 19, 20)
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Specification