MASK MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING THE SAME

• US 20170115556A1
• Filed: 10/21/2016
• Published: 04/27/2017
• Est. Priority Date: 10/22/2015
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Shim, Woo-seok, Liang, Wenqing
• Application Number:
  US15/299,558
• Publication Number:
  US 20170115556A1
• Time in Patent Office: Days
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A mask manufacturing method and a semiconductor device manufacturing method are provided. The methods form a plurality of dummy patterns without any change in hierarchical structure to reduce a turn-around time (TAT) and a performance of a system. The mask manufacturing method includes designing a layout of a main pattern, performing integrated optical proximity correction (OPC) on the layout, delivering design data, obtained through the integrated OPC, as mask tape-out (MTO) design data, preparing mask data based on the MTO design data, and exposing a substrate for a mask, based on the mask data, wherein the performing of the integrated OPC includes generating a dummy pattern in a state of maintaining hierarchical structure.

Claims

1. A method comprising:

designing a layout of a main pattern;

performing integrated optical proximity correction (OPC) on the layout;

obtaining design data from the result of the integrated OPC;

delivering the design data as mask tape-out (MTO) design data;

preparing mask data, based on the MTO design data; and

exposing a substrate to form a mask, based on the mask data,

wherein the performing of the integrated OPC comprises generating a dummy pattern in a state of maintaining hierarchical structure.

2. The method of claim 1, wherein the performing of the integrated OPC comprises:

analyzing a structure of the layout;

separating templates, based on the analysis;

generating the dummy pattern after separating the templates;

generating a sub-resolution assist feature (SRAF); and

performing OPC on the templates.

3. The method of claim 2, wherein the dummy pattern is generated in a state of maintaining the hierarchical structure in each of the templates.

4. The method of claim 2, wherein the dummy pattern and the SRAF are generated in the same template.

5. The method of claim 2, wherein the templates are distinguished from and separated from each other, based on an influence range of the main pattern.

6. The method of claim 2, wherein

the main pattern is a pattern corresponding to a circuit pattern of a semiconductor device,

the dummy pattern is an auxiliary pattern for preventing a patterning error of the circuit pattern and is formed in the semiconductor device, and

the SRAF is an auxiliary pattern for compensating for an OPC deviation caused by a density difference between patterns and is not formed in the semiconductor device.

7. The method of claim 1, wherein the performing of the integrated OPC comprises receiving data corresponding to the layout, which does not include the dummy pattern.

8. The method of claim 1, further comprising:

after the designing of the layout, performing a design rule check (DRC),

wherein the performing of the DRC comprises;

proceeding to the performing of the integrated OPC when a predetermined reference is satisfied; and

proceeding to the designing of the layout when the predetermined reference is not satisfied.

9. The method of claim 1, further comprising:

after the performing of the integrated OPC, performing OPC verification,

wherein the performing of the OPC verification comprises;

proceeding to the delivering of the design data as the MTO design data when a predetermined reference is satisfied; and

proceeding to the performing of the integrated OPC when the predetermined reference is not satisfied.

10. The method of claim 1, further comprising:

exposing a semiconductor substrate using the mask to form a semiconductor device.

11. A method of manufacturing a semiconductor device, the method comprising:

designing a layout of a main pattern;

receiving data corresponding to the layout;

performing integrated optical proximity correction (OPC) including generating a dummy pattern in a state of maintaining a hierarchical structure and generating design data;

delivering the design data as mask tape-out (MTO) design data;

preparing mask data, based on the MTO design data;

exposing a substrate to form a mask, based on the mask data; and

forming a semiconductor device through a lithography process using the mask.

12. The method of claim 11, wherein the performing of the integrated OPC comprises:

analyzing a structure of the layout to separate templates;

generating the dummy pattern and a sub-resolution assist feature (SRAF) in each of the templates; and

performing OPC on the templates.

13. The method of claim 12, wherein the dummy pattern and the SRAF are generated in the same template.

14. The method of claim 11, further comprising:

after the designing of the layout, performing design rule check (DRC); and

after the performing of the integrated OPC, performing OPC verification,

wherein

the performing of the DRC comprises proceeding to the performing of the integrated OPC or the designing of the layout according to whether a predetermined reference is satisfied, and

the performing of the OPC verification comprises proceeding to the delivering of the design data as the MTO design data or the performing of the integrated OPC according to whether the predetermined reference is satisfied.

15. A method, comprising;

designing a layout of main patterns of a mask;

determining the layout into a plurality of templates based on the structure of the layout;

generating dummy patterns in the respective templates;

performing optical proximity correction in the patterns of the respective templates;

delivering mask tape-out design data based on the result of the optical proximity correction; and

forming a photomask with the mask tape-out design data.

16. The method of claim 15, further comprising:

exposing a substrate using the photomask to form a photoresist pattern on the substrate;

etching the substrate using the photo resist pattern as an etching mask; and

dividing the substrate into a plurality of chips.

17. The method of claim 16, further comprising:

forming a semiconductor package with a first chip of the plurality of chips; and

mounting the package on a board to form an electronic device.

18. The method of claim 15, further comprising:

generating sub resolution assist features in the respective templates before performing the optical proximity correction.

19. The method of claim 15, further comprising:

performing a design rule check before the determining the layout into the plurality of templates.

20. The method of claim 15, wherein the determining the layout into the plurality of templates includes considering an influence range between adjacent patterns.